Lithography Workshop Update

Increases in lithography productivity may require higher equipment utilization.

Ruth DeJule, Associate Editor -- Semiconductor International, 1/1/1998

Lithography Workshop Update

The 34th annual Interface conference, sponsored by Olin (Norwalk, Conn.), was held in San Diego, Calif., in November. Current lithography issues covered included overlay accuracies, CD uniformity, lithography tools and simulation. The keynote speaker, SEMATECH's Gene Feit, reviewed Next-Generation Lithography Options, a SEMATECH workshop held in Colorado Springs, Colo., that covered post-optical lithography beyond 193 nm. The workshop, by invitation only, included about 100 representatives worldwide. The focus was six to nine years out, at 100 nm to 70 nm design rules. Two or three lithography techniques that would have a better chance of success emerged from the workshop, though they have yet to be announced.

The five techniques discussed were multiple electron beam direct write (MEBDW), ion projection lithography, SCAPEL, EUV and X-ray. In terms of resist sensitivity, SCAPEL, EUV and ion projection lithography appear to be in good shape and have demonstrated 70 and 80 nm linewidths. For these techniques, DUV and even i-line resists may work. MEBDW has the furthest to go.

Speculation about the possible short lifetime of 193 nm technology is causing some companies, such as Mitsubishi and Siemens, to bypass 193 altogether. Olin, however, believes this technology will be the successor to 248 nm. Showing its commitment, Olin will be supplying 193 nm resists in early 1998, said Sydney Slater, Olin's 193 nm venture manager.

The central issue, however, is not resists, but photomask technologies, Feit noted. These techniques require very complicated masks, such as membrane or multiple layers. SEMATECH's board will be meeting to make a final decision.

Keeping Pace with Moore's Law

Quality, quantity and efficiency are three critical factors in boosting productivity (Table 1). Over the past 20 years, emphasis has been on the process, the key issues being quality and yield. However, once yields reached 90% and 95%, throughput became the focus. Now, twice as many wafers can be processed out of the same footprint. Efficiency is the next productivity lever, according to Pete Steege, microlithography division marketing manager at FSI (Chaska, Minn.).

Table 1. Productivity in Lithography
Quality DUV yields Production-capable 193 nm Mask technology Overlay	Quantity Field size Throughput 300 mm wafers	Efficiency Utitlization Resist consumption Footprint

Efficiency is the percent of time equipment is making product, which, according to SEMATECH data from one fab, is only 43%. Of the 57% downtime (systems sitting idle), setup time and test wafers make up ~40%, with tool reliability contributing only about 7%. If it is assumed that 43% applies to each piece of equipment, the most expensive equipment -- the combined stepper and track systems -- most likely make product less than 40% of the time. Efficiency is clearly the next area to improve productivity.

One solution to increasing utilization is through more efficient track systems. At FSI, advanced scheduler algorithms are implemented to eliminate flush and fill times and to run test wafers simultaneously with production wafers.

Track systems run through ~10 process steps per wafer. An anti-reflective coating requires an additional coat, bake and chill cycle. To change lots, there is typically a 10 min wait for the track and stepper to flush out all remaining wafers and another 10 min to fill. Some fabs change recipes more frequently than others. If recipes change twice per shift, which could be considered typical, utilization loss would be 12%.

While lot chaining the seamless following of one completed lot after another is currently done for lots with like recipes, once the recipe is changed, the line must emptied before the next lot can be started. For example, Lot 1 may be a DRAM level 1 recipe followed by a different level on the chip for Lot 2, so the recipe changes. The equipment cannot chain that. The first lot must first go completely through the system. With nonlinear handling algorithms, each station can automatically be reset independently, thus eliminating flush and fill, even if the flow changes.

Similarly, processing test wafers, which accounts for 13% of utilization loss, can be run simultaneously with production wafers with these algorithms. While throughput would go down, the machine is still producing wafers, Steege noted.

On the fab level, the concept of OEE brings out another productivity lever: equipment footprint. For a given throughput, the smaller the equipment, the more wafers per hour per fab. To address this issue, resist vendors have stacked process stations and reduced machine length over width in accordance with the stepper, which typically dictates a lithography cell's width.

One area yet to be addressed is the absence of wafers or operators at the tool. Lithography cells can process up to six lots unattended by an operator. However, as throughput approaches 100 wafers/hr and turnaround times 15 min, idle time becomes more of an issue. One equipment solution is to increase the queuing capacity in the track by increasing the number of cassette nests and providing lot and recipe queuing capability software.

Erratum

Technology Modeling Associates (TMA, Sunnyvale, Calif.) would like to express appreciation to Steve Brainerd, currently with Maxim Integrated Products (Beaverton, Ore.), for providing the experimental data for OPC Simulation, which appeared in September's lithography news.