Boron Penetration in Dual Gate Process Technology

Zhixu Zhou -- Semiconductor International, 1/1/1998

At A Glance . . . Today's submicron VLSI process integration commonly utilizes a dual gate CMOS process to achieve surface n- and p-channel MOSFETs. Boron penetration from p+ doped polysilicon gates can cause degradation in device performance. Understanding boron penetration in p+ polysilicon gate p-MOSFETs is critical in order to design a robust process.

For optimal logic-gate performance, the threshold voltage of n- and p-channel devices in CMOS circuits should have comparable magnitude. In addition, for maximum current-drive capability, the threshold voltage should also be as low as possible (limited by noise margin and subthreshold leakage considerations).1 For 5 V CMOS technologies, desirable threshold voltages are ~0.6 to 0.8 V for NMOS and -0.6 to -0.8 V for PMOS, respectively. For n⁺ doped polysilicon gate technology, the work function difference between n⁺ doped polysilicon and p-type substrates is ideal for n-channel devices since it provides threshold voltages between 0.6 to 0.8 V for reasonable values of channel doping and gate oxide thickness. However, for p-channel devices, the threshold voltage is more negative than -0.8 V. Hence, both n- and p-channel MOSFETs (metal oxide semiconductor field effect transistors) require p-type channel threshold adjust implants to produce the proper threshold voltages for VLSI applications. Such implantation makes the p-MOSFET into buried-channel devices.

Fig. 1. Energy-band diagram of p-MOSFETs with n⁺ doped polysilicon gate: (a) without p-type threshold voltage adjust implant, (b) with p-type threshold voltage adjust implant.

Figure 1 shows the band diagram of a p-MOSFET with an n-type polysilicon gate, with and without the p-type channel threshold voltage adjust implant. It is clear that with n⁺ doped polysilicon gate technology, PMOS needs a p-type threshold voltage adjust implant to lower its threshold voltage to appropriate values. The p-type Vt adjust implant creates a PN junction and depletion region near the channel surface. This causes the potential minimum for holes to be located away from the surface, and the majority of the holes flow along a buried channel where the potential minimum exists, away from the channel surface. This is termed a "buried-channel" device.

Buried-channel devices are more prone to short-channel effects, such as threshold voltage lowering in the submicron regime and poor subthreshold turnoff characteristics compared to surface-channel devices.2 It can be argued that since the channel is buried below the surface, the gate voltage partially loses its ability to control the channel charge. Another way to interpret this effect is that the depletion region formed by the PN junction in the substrate forms an additional depletion capacitance, leading to an effective gate oxide capacitance decrease and poorer gate controlling ability.

Various approaches have been proposed to overcome these short-channel effects, such as raising the threshold voltage³ and using extremely shallow channel implants and source/drain junction depths.⁴ On the other hand, buried-channel devices have also been advocated as a better choice for short-channel transistors.⁵

Extensive research has compared the performance between surface-channel and buried-channel devices in the submicron regime. The general consensus today is that surface-channel devices have less threshold voltage lowering than buried-channel devices. The subthreshold swing is also worse for buried-channel devices. The leakage current of a buried-channel device in the off-state (V_GS = 0 V) is about three to four orders of magnitude higher than that of a surface-channel transistor.⁶ This is partly due to the fact that buried channel is further from the gate/substrate interface, therefore the gate does not control the channel as effectively as the surface channel devices can. In particular, drain-induced barrier lowering⁷ becomes more significant in buried-channel devices.

One advantage of buried-channel devices is its higher carrier mobility because of less surface scattering. However, since the channel is farther away from the surface, the effective gate capacitance is reduced and the improvement in carrier mobility can- not be fully utilized.

Because of the differences between surface- and buried-channel devices (analyzed in Ref. 6), it has been largely concluded that buried-channel design is always more susceptible to short-channel effects and has undesirable subthreshold characteristics. As a result, most CMOS technology today employs the dual gate approach to implement surface channel devices forn- and p-MOSFETs.

In order to realize a surface-channel p-MOSFET, the polysilicon gate needs to be doped p-type (Fig. 2). After thermal oxidation to form the gate oxide, polysilicon is normally deposited using a low-pressure chemical vapor deposition (LPCVD) process. The gate can also be an amorphous silicon structure, depending on the LPCVD process conditions. After gate pattering, usually done in an RIE etch process, self-aligned source/drain implantation is done. This implantation step also simultaneously implants the polysilicon gate and forms the p⁺ polysilicon gate p-MOSFET. The implant species are usually boron or boron-difluoride (BF₂). For submicron and deep submicron devices, BF2 is commonly used because of its higher atomic weight in order to achieve shallow source/drain junctions. However, the incorporation of fluorine into the polysilicon gate poses additional problems.

Fig. 2. Process to realize p⁺ doped polysilicon gate p-MOSFET: (a) gate oxide formation and polysilicon gate deposition, (b) polysilicon gate patterning and source/drain implantation.

Boron penetration in p⁺ gate

As evident from Figure 2, the boron in the polysilicon gate material can be driven into the gate oxide, or even into the substrate, if substantial thermal cycles exist after the source/drain implantation. Although low thermal budget back-end processing is always desirable, its complete elimination is not possible. These include polysilicon gate oxidation, dopant activation, spacer formation and interlevel-dielectric densification and reflow, etc.

The signature of boron penetration in p-MOSFET is often recognized as threshold voltage instability and subthreshold swing degradation. Gate oxides with boron penetration also exhibit degradation in its oxide reliability,8-10 in particular, reduction in oxide breakdown characteristics and increase in charge trapping rate.

p-MOSFET performance and oxide degradation

When boron is diffused into the gate oxide from its p⁺ doped polysilicon gate, it acts as a negative charge in the gate oxide, leading to positive threshold voltage shifts. Once boron penetrates the oxide into the substrate, it compensates the channel threshold voltage adjust implant, which is of the opposite type species (e.g., phosphorous). The channel doping compensation, especially near the surface below the gate oxide, causes substantial degradation in subthreshold characteristics apart from the threshold voltage increase.

Gate Degradation

Click for larger image.

Fig. 3. Shown is p+ doped polysilicon gate p-MOSFET degradation because of boron penetration: (a) threshold voltage and subthreshold swing instability, (b) transconductance degradation.

Figure 3 shows experimental data for p-MOSFET threshold voltage, subthreshold swing and transconductance degradation. The subthreshold swing is defined as the gate voltage necessary to lower the drain current by one decade in the subthreshold regime. It is given by the following:

Threshold voltage is extracted using the linear extrapolation technique, with the maximum slope obtained from the transconductance. Extracted subthreshold swing and threshold voltage values are shown in the insert of the I_d-V_G plot. The device has width/length = 24 µm/0.7 µm. All samples have thermally grown oxide, with a thickness of 92 Å. All samples also received a BF₂ source/drain implant with a dose of 5 x 10¹⁵ cm^-2. Some wafers also received 750°C and 850°C thermal drive-in anneal after spacer formation to accelerate the boron penetration. Both drive-in processes are performed for 15 min in a dry N₂ ambient. It can be clearly observed that with increasing temperature, boron penetration effects become more profound and result in large increases of threshold voltage and significant degradation in subthreshold swing and transconductance. The instabilities of p-MOSFET devices because of boron penetration also raise concern for better process control and the need to minimize the back-end thermal budget and its variation.

The penetration of boron into the gate oxide and substrate region also has adverse effects on gate oxide integrity. Shown in Figure 4 is the cumulative percentage failure of capacitor charge-to-breakdown for a thermal oxide and oxide with 850°C, 15 min boron drive-in. Boron penetration into the gate oxide and Si substrate causes the overall oxide reliability to degrade. It has been reported¹⁶ that boron penetration through a gate oxide and into Si substrate also causes a drastic degradation in the Si/SiO₂ interface. The effect of interface degradation because of boron penetration has been revealed by using high-resolution transmission electron microspy (HRTEM).

Effect of fluorine

In general, the incorporation of fluorine into a gate oxide, either at the oxide/substrate interface or in the bulk of the oxide, improves the oxide reliability with enhanced immunity against hot-electron injection and reduced interface trap density.^11-14 Increased oxide charge-to-breakdown (Q_bd) and reduced leakage current can be achieved by using a HF-last pre-oxide growth cleaning process. The improved oxide reliability is the result of several factors: the passivation of the Si surface, reduced native oxide growth and reduced surface microroughness. The HF-last pre-oxide cleaning process provides a sufficient amount of hydrogen passivation, preventing native oxide growth and preserving an atomically smooth Si/SiO₂ interface. Some Si-F bonds are also formed, which possibly relaxes the strain distribution near the Si/SiO₂ interface, leading to an improved resistance against hot-carrier damage.

Although it is advantageous to incorporate fluorine into a gate oxide for improved reliability, fluorine adversely affects the device by significantly enhancing boron penetration in p⁺ doped polysilicon gate p-MOSFETs.¹⁵ A grain boundary dominated diffusion model has been established¹⁵ that agrees well with the experimental data. For BF₂ implanted p+ polysilicon gates, it is found that as the post implant anneal temperature increases, the fluorine concentration at the gate/SiO₂ interface increases. This is accompanied by higher boron concentration at the gate/SiO₂ interface. Various experiments of co-implanting polysilicon gate material with boron and different doses of fluorine also concluded that fluorine incorporation significantly enhances boron diffusion along grain boundaries, consequently causing more boron penetration into the gate oxide and substrate region. Hence, it is beneficial to use boron instead of BF₂ as the implant species to avoid the fluorine enhanced boron diffusion along the polysilicon grain boundary. However, BF₂ is widely used in today's submicron devices to achieve shallow source/drain junctions because of its large molecular weight (thus better implant stopping capability).

Fig. 4. Charge-to-breakdown characteristics for thermal oxides with different amounts of boron penetration. constant current density = 100 mA/cm².

Boron penetration reduction

There are two main approaches to reduce boron penetration. Within each approach, many variations of process integration exist. One method is to modify the polysilicon gate structure to reduce boron penetration; the other approach is to modify gate oxide to reduce boron penetration. Other techniques such as co-implanting the polysilicon gate with phosphorous, silicidation of polysilicon gate, etc., have also been proposed.

The polysilicon is commonly deposited using the LPCVD process. The gate material's microstructure can be readily modified through different process parameters. One common way to reduce boron penetration is to increase the grain size of the polysilicon such that there are fewer grain boundaries available for boron diffusion, especially fluorine-enhanced boron diffusion. Depositing Si films in an amorphous state rather than in a polycrystalline state also significantly reduces fluorine-enhanced boron penetration. Amorphous Si (a silicon) is usually deposited at a lower temperature (e.g., T ~550°C), while polysilicon films are usually deposited at a higher temperature, typically higher than 600°C. This approach has proved to be a very effective method to reduce boron penetration. Amorphous si gate structures such as stack-layered Si gate structures and other variations of forming the gates structures have shown excellent ability to reduce the adverse boron penetration effect.^{10, 16}

Another commonly used approach is by nitridation of the gate oxide. A nitrogen-containing bond structure is an excellent diffusion barrier against most dopants. By incorporating nitrogen into the gate, the boron (or BF₂ complex) diffusing from the gate is blocked before reaching the Si substrate. N₂O nitridation is commonly used because of its ability to reduce boron penetration and its improved gate oxide reliability compared with thermal oxide. Recently, nitridation in nitric oxide (NO) has been proposed and has shown significant improvement in gate oxide reliability and resistance to hot-carrier induced degradation.17,18 Because more nitrogen is incorporated at the Si/SiO₂ interface using NO nitridation than N₂O nitridation, it is reasonable to believe that NO nitridation will reduce boron penetration as well.

Effects in N₂O Nitrided Oxide

Click for larger image.

Fig. 5. Effect of boron penetration in N₂O nitrided oxide: (a) current-voltage characteristic, (b) transconductance.

Shown in Figure 5 are current-voltage characteristics and transconductances for transistors with N₂O nitrided gate oxides. The gate oxide is grown at 950°C in a pure O₂ ambient, and subsequently annealed in pure N₂O ambient for 30 min at the same temperature. The final oxide thickness is 92 Å, determined by ellipsometry. All samples received BF₂ source/drain implantation of 5 x 10¹⁵ cm^-2. Some wafers also received 750°C and 850°C thermal drive-in after spacer formation to accelerate the boron penetration. Samples also received excess thermal drive-in to accelerate the boron penetration. Obviously, boron and BF₂ diffusion from the p⁺ doped polysilicon gate through the gate oxide are blocked at the Si/SiO₂ interface because of the nitrogen incorporation at the gate/substrate interface.

Another significant improvement is achieved in gate oxide reliability. Figure 6 shows the charge-to-breakdown comparison between thermal gate oxide and N₂O annealed gate oxide. It is clear that nitrogen incorporation at SiO₂/Si interface significantly improves gate oxide reliability. Boron penetration-induced gate oxide reliability degradation is also much reduced for N₂O annealed oxide.

Fig. 6. Charge-to-breakdown comparison for thermal gate oxide and N₂O-annealed gate oxide. Constant current density = 100 mA/cm².

Boron diffusion in thin oxide

It is useful to estimate the amount of boron diffusion under different
conditions. In Reference 19, a comprehensive model of boron diffusion in thin oxide was developed. The model is based on the random-walk theory, and it is argued that boron diffusion preferably occurs along the peroxy linkage defect (PLD). Dependence of boron diffusion on fluorine content, oxide thickness and nitrogen content are all included in the model.

The boron diffusion constant can be modeled with the following equation:¹⁹

D_B[N] includes the effects from gate oxide nitridation and thin oxide. Fluorine incorporation is also taken into account in Equation 2 through the second term. AC is a pre-factor and is assumed to be equal to 2.75 * 10^-10 cm³/s. K'_N is the reaction constant and is assumed to be 5 * 10^-6. Boron diffusion dependence on oxide thickness is modeled through a characteristic length, l_c.

Based on the above equations, boron diffusion in thin oxides can be readily modeled. Figure 7 shows the effect of fluorine content on diffusion length. Using the peroxy linkage defect as the basis for boron diffusion, it is proposed that fluorine introduced into a oxide creates additional PLDs, which consequently enhances boron diffusion. Boron diffusion is significantly enhanced when the fluorine dose exceeds 1 * 10¹³ cm^-2.

Fig. 7. The role of fluorine in enhancing boron diffusion in thin oxide.

Figure 8 illustrates the effect of gate oxide thickness and temperature on boron diffusion. It has been proposed that SiO is formed at the Si-SiO₂ interface during oxidation of Si. The SiO species are metastable since partial decomposition into Si and O atoms occurs at elevated temperatures as SiO diffuses away from the interface. The lowest enthalpy decomposition reaction involves SiO and SiO₂ in which a PLD is formed.¹⁹ This implies that there would be more PLDs at the interface than in the bulk. Therefore, boron diffusion should be accelerated in thin oxides, as is clearly seen in Figure 8.

Fig. 8. Contour plot of boron diffusion length as a function of gate oxide thickness and diffusion temperature. Anneal time is 15 min; nitrogen content is assumed to be 4%.

Conclusion

It is clear that boron penetration has profound ef-fects on p-MOSFET transistor device characteristics. Excessive boron penetration not only seriously impacts device performance, but also degrades gate oxide reliability. The Si/SiO₂ interface is also significantly degraded and its resistance against hot-carrier induced interface generation lowered when boron penetrates through oxide into the Si substrate. Hence, boron penetration must be carefully considered for submicron VLSI devices.

Boron penetration is much enhanced for p-MOSFETs with BF₂ implanted polysilicon gates. Because of the need to utilize BF₂ implantation in the submicron regime to achieve shallow junctions, it becomes mandatory to reduce boron penetration to preserve the desired device characteristics and gate oxide quality. Various methods have been proposed and successfully implemented to reduce boron penetration. By modifying the gate material, such as making it amorphous, fewer diffusion boundaries are available, and boron penetration is reduced. Nitridation of the gate oxide also greatly reduces boron penetration, through nitrogen incorporation and its diffusion blocking capability. In addition, nitrided gate oxides have improved charge-to-breakdown because of the stronger bonds formed at the SiO₂/Si interface because of nitrogen incorporation.

Boron diffusion can be readily estimated through the models established in reference 19. By examining the effect of different parameters on boron penetration, such as gate oxide thickness, amount of fluorine, nitrogen incorporation, etc., boron penetration effects can be predicted and used to assist the design of a robust process.

References

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