Speeding the Transition to 0.18 µm
Laura Peters -- Semiconductor International, 1/1/1998
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At a Glance | | |
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Expected to take place in less than two years, the transition from 0.25 µm to 0.18 µm is already shaping up as the fastest technology transition in semiconductor history. In 1999, leading-edge fabs will begin production of 0.18 µm devices microprocessors operating at gigahertz speeds and DRAMs storing a gigabit of information. The newly released 1997 National Technology Roadmap for Semiconductors reflects the increased rate at which semiconductor companies are moving to new device generations now two years relative to the industry's traditional three years (Table 1). Acceleration of this pace is having profound effects on all aspects of IC design and manufacturing.
Table 1. 1997 SIA Roadmap for Semiconductors
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| Fig. 1. The laws of scaling twin-well CMOS devices to 0.18 µm are causing increased use of high-density plasma CVD for dielectrics, general shifts from sputtered metals to metal CVD and increased use of CMP. |
A surprising and perhaps un-precedented number of new technologies will enter the 0.18 µm fab lines. These include the establishment of a production-worthy lithography platform for KrF exposure tools and resolution enhancements. High-density plasma (HDP) sources are enabling good metal step coverage and filling capability. Shallow trench isolation becomes essential at 0.18 µm, as do a number of new ion implantation steps, rapid thermal processes and CMP. Copper metalization will make its debut in manufacturing at 0.18 µm, used first on the top levels of metal for leading-edge microprocessors. Alternative die-lectrics will be slowly adopted into mainstream manufacturing of a variety of devices, driven by both performance and thermal budget reasons.
Today's state-of-the-art
An example of current state-of-the-art manufacturing capability is illustrated in the lead photo. This SEM shows a cross section of IBM's model 604e microprocessor, a production device that was fabricated using 0.18 µm feature sizes, six levels of aluminum interconnect, tungsten plugs, CMP and damascene of the local interconnect, in this case, tungsten. Although copper interconnects were not used on this device, both IBM and Motorola have announced intentions to use copper interconnects on 0.18 µm generation microprocessors (see "Copper Goes Mainstream: Low-k to Follow," Semiconductor International, November 1997, p. 67).
Beyond establishing production-worthy lithography for printing these fine features, perhaps the next greatest challenge at 0.18 µm involves risk management associated with integrating new materials into the process. As Sam Broydo, managing director for Process Sequence Integration at Applied Materials (Santa Clara, Calif.), explained, "It took the company several years of experience with fluorinated silicon dioxide to create a robust, production-worthy film that chipmakers could confidently integrate into their devices." In production, low-k fluorinated oxides deliver a dielectric constant of approximately 3.5 or 3.6.
Lithography: The greatest challenge
The switch from i-line lithography to DUV (KrF at 248 nm, ArF at 193 nm) provides enormous challenges in every area of the lithography cell from maskmaking to metrology. Both 0.25 µm and 0.18 µm share common challenges regarding the reduced process window at 248 nm (relative to the capabilities of i-line systems) and the need to effectively bring resolution-enhancement techniques into a production environment. "Management efficiency in the lithography cell has a high impact on the cost effectiveness of your overall manufacturing process and ultimately yield," explained Ed Grady, vice president and general manager of the RAPID Division of KLA-Tencor (San Jose, Calif.). Grady continued, "At 0.25 and 0.18, the most fundamental change is the lowering of the k1 factor to get higher resolution, through the use of optical proximity correction masks, phase shifting masks, etc. At lower k1, the defect size that you need to detect gets smaller." KLA-Tencor uses analysis software to simulate whether a mask defect will print given a specific layout design. Such simulation is essential at 0.18 µm as some estimate the investment in a 0.18 µm mask set could run as high as a million dollars.
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| Fig. 2. The 0.18 µm requirements border the cusp between maximum extension of KrF exposure and the need to use ArF tools. (Source: Hitachi Ltd.) |
As shown in Figure 2, the requirements for 1Gb DRAM lithography fall right on the cusp between KrF capabilities with resolution enhancement and the need for ArF (193 nm) exposure tools. While it is beyond the scope of this article to explore DUV requirements in detail, look for feature articles in the February issue of Semiconductor International on advanced lithography challenges and special requirements of 300 mm lithography.
Precision doping
There are essentially four new applications in ion implantation required for 0.18 µm devices. "The most important is the scaling of the n+ and p+ source/drains, specifically the PMOS transistors, where revolutionary changes in ion implanter or beamline designs are needed to attain acceptable throughput," explained Bob Simonton, director of marketing for Eaton's Ion Implantation Division (Beverly, Mass.). In addition to ultrashallow junctions, companies are implementing a variety of implants for channel engineering, including retrograde wells, triple wells and high-tilt-angle punchthrough stoppers. Individual doping of the poly gates also becomes a mainstream application at 0.25 µm and essential at 0.18 µm.
According to the new SIA Roadmap, ultrashallow junctions for 0.18 µm devices will range in depth from 36-72 nm, going to 30-60 nm for the 0.15 µm generation. These junctions require high-current, low-energy implants and precise process integration with the subsequent RTP activation step. "The integrated process to achieve dopant activation and control diffusion is a solved problem for 0.25, but it's still a challenge for 0.18," Simonton said. He added that while many process engineers would like to stay with the BF2 chemistry for p+ S/D junctions, a change to elemental boron is needed because of fluorine's propensity to enhance boron diffusion through the gate oxide to the p+ transistor, causing uncontrolled shifts in threshold voltage. Simonton predicted that plasma immersion and mass analyzed ion implanters will compete directly for S/D formation at the 0.15 µm generation. At that time, elevated S/D approaches for silicide contact formation will also be evaluated.
To maintain high device drive currents while minimizing short channel effects, new single-wafer, high-tilt-angle implanters are allowing optimization of the transistor channel. This approach adds two high-tilt implantation steps to the process flow, one each for p+ and n+ transistors (high-tilt punchthrough stopper implants).
Many IC manufacturers first began using high-energy implanters to form retrograde wells (doping highest at bottom of well) on the 0.25 µm or even 0.35 µm devices. New implanters are capable of providing a chain of implants, performing all the well doping including the threshold adjust implant in a single system. This approach significantly reduced the number of process steps and cycle time.
Now certain devices, particularly embedded technologies, are requiring the next logical extension of this technology to triple wells that further isolate the p-well from the p-substrate. "Triple wells are important for flash memory, SRAM, embedded devices and especially embedded flash in microprocessors," Simonton said. He added, "Key to the formation of these wells is close process control between photoresist stabilization, implantation and subsequent stripping, as thick resist (2-5 µm) is needed for high-energy ion implantation." High-dose buried layers, also formed using high-energy implanters, are designed to reduce device latch-up. These layers can provide a cost-effective alternative to epi wafers, especially as the variety of functions present on a chip increases. Current estimates show that a 300 mm epi wafer costs ~$900-1000 each in high volume, relative to $600-700 for polished silicon.
Changes in dielectrics
Though conventional dielectrics such as plasma-SiO2, TEOS/ozone-based and spin-on glasses will continue to be used, at 0.18 µm many of the dielectrics are being replaced either for performance or thermal budget reasons. Boron phosphosilicate glass (BPSG) is gradually being replaced by PSG, deposited by high-density plasma (HDP) CVD, and LOCOS oxidation is being replaced by shallow trench isolation, also deposited using HDP sources. The capacitor dielectric in DRAMs is changing from oxynitrides to high-k (20-30) tantalum pentoxide (Ta2O5) with rough poly capacitor plates. At this time, companies appear to be pushing out the use of barium strontium titanate (BST) to future generations of DRAMs. Reasons for this delay include the very reactive nature of BST, the need to control precisely the stoichiometry of the material and difficulties in integrating BST with various new electrode materials.
Regarding the move away from BPSG for pre-metal dielectric, Farhad Moghadam, general manager of dielectric deposition and emerging technologies at Applied Materials, explained, "If you can deposit a PSG film at 400-500° using HDP and then planarize it using CMP, you've eliminated the high temperature reflow, and you've also eliminated boron from the process, which was always difficult to control."
HDP sources also enable the use of aluminum plugs vs. tungsten, which reduces resistance between metal layers. HDP CVD layers are also beneficial because of the film's likeness to thermal oxide. Moghadam said, "HDP CVD is silane based, which is much easier to polish than TEOS-based films." TEOS-based films typically have a 6:1 etch rate difference than thermal oxide, as opposed to 1.2:1 for HDP films. Another, perhaps more important feature of the high-density sources is their extendibility to finer device geometries. Multigenerational tools in CVD, PVD and etch will be essential to keeping the cost of manufacturing at reasonable levels.
At 0.25 µm, the most commonly used approach for low-k dielectrics are fluorinated oxides (HDP-SiOF) and hydrogen silsequioxane (HSQ), with k=3.5 and k=2.9, respectively. Companies will continue to use these inorganic dielectrics at 0.18 µm, with a few manufacturers of microprocessors going to even lower k organic materials. "It appears that spin-on inorganic dielectrics like HSQ will be one of the materials of choice," commented Mike LaFleur, manager of technology in strategic marketing for Lam Research Corp. (Fremont, Calif.). He added, "The organic dielectrics should enter production around the year 2000."
The benefits of moving to low-k dielectrics are significant. As Broydo explained, "Overall, capacitance reduction is more important than the decreased resistance provided by copper, because capacitance affects the device in three ways speed is increased due to lower RC delay, crosstalk is reduced because of the reduced capacitance between parallel lines and power dissipation is reduced as well." For this reason, chipmakers are evaluating the benefits of making dielectric changes, such as replacing SiO2 with fluorinated oxide, based on the device itself and its sensitivity to capacitance.
Copper and other metalization changes
Because of the vast array of options regarding copper metalization choosing a damascene structure, choosing the barrier layer, seed layer and copper deposition method, integrating CMP, etc. the industry will likely take a stepwise approach to copper and low-k. Progress is also transpiring in copper etch. According to LaFleur, "People have successfully etched 0.25 µm lines and spaces on copper, but to do that in manufacturing with the complexity of devices in the future may not be viable." Regarding damascene, Broydo commented, "People used to talk about doing aluminum damascene so there would be practice in doing damascene. But already these same people are saying, 'no, it's too late to do damascene for aluminum; we'll have to do damascene for copper.' "
Aluminum via fill is finding increasing application at 0.18 µm, especially for reducing cost in DRAM devices. Expect to see a variety of PVD/CVD schemes used in production over the next several years. To fill higher aspect ratio vias, lower pressure sputtering sources have been developed. Beyond that, Applied Materials has developed a new CVD aluminum technology that partially fills the via, followed under vacuum by a PVD aluminum fill at low temperature. "One key advantage of this CVD/PVD technique over a CVD-only fill is that it allows users to dope the aluminum," explained Moris Kori, managing director in Applied's Metal Deposition Product Business Group. "Using a thin CVD layer, followed by sputtering, you don't have to worry about in situ doping CVD aluminum a difficult process which people have pursued for a while," he said.
For liners and barriers, various CVD metals have been developed. Applied Materials also developed a new PVD technology using an ionized metal plasma. Kori added that this approach effectively extends the usefulness of sputtering technology for at least one more generation. "Most people thought that after collimation, we would have to go to metal CVD across the board. This technology effectively bridges that gap," he said.
Yield management and operational effectiveness
As semiconductor manufacturers continue to push manufacturing capabilities in pursuit of shorter time to market and to capture the high end of the average selling price (ASP) curve, one unfortunate result is the premature transfer of processes to production. As Tom Long, vice president and general manager of KLA-Tencor's Yield Management Consulting Group, explained, "At 0.25 and 0.18 µm we. re seeing a lot of processes being transferred with process integration issues, so production personnel are saddled with trying to fix process integration problems that should have been solved during the development phases for the device." For this reason, IC manufacturers are beginning to depend more on equipment vendors for not only process development but also integration of key processes.
Long explained that while yield improvement from the standpoint of reducing random defectivity is the focus of production, often today the fab has as many systematic defects as random defects, "particularly as today's processes push the limits of lithography," he said. "In the logic area, we find that the systematic defect component is comparable to the random defect component." He noted that in memory manufacturing where typically one product is being fabricated, the majority (60-65%) of defects are random defects.
As a result, yield ramping becomes more complex. As shown in Figure 3, as the industry progresses to subsequent device generations, both the starting yield rate (when the device enters production) and the yield ramping rate are critical, particularly as the profitability of DRAM manufacturing has plummeted in recent years.
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| Fig. 3. Each new device generation requires that yield ramps become steeper and probe yields at transfer from pilot line to production become higher. (Source: VLSI Research) |
Long added that while most of the industry uses Intel as an example of fast yield ramping, many companies in the semiconductor industry do not have the resources to prove-out yield problems in the development lab, as Intel has. "In cases where processes have been licensed, the infrastructure may not exist for companies to rectify yield issues in a timely manner." Long's group has benchmarked more than 80 production fabs to date, enabling some companies to improve yields by 40-50% in less than six months. Key to this yield improvement is the rapid identification of systematic and random defects, so that engineering resources can focus on fixing yield problems.
David Guidry, product manager at Knights Technology (Sunnyvale, Calif.), emphasized the importance of built-in analysis capabilities to yield managers in the fab. "Engineers want meaningful information, results and correlations that have been automatically calculated using, for instance, spatial pattern recognition and data mining techniques," he explained. "As the volume of defect inspection and analysis data continues to grow, the need for automated data analysis and problem diagnosis becomes increasingly critical," he added.
The 300 mm question
Initial industry consensus indicated a simultaneous move to 0.25 µm technology and 300 mm wafer processing. It now appears that 300 mm may be pushed out to at least the 0.18 µm generation. DRAM manufacturers will be among the first to implement 300 mm. General scaling of PVD, CVD and etch processes appears very promising. Lithography and the cost-effectiveness of the lithography cell is the most important issue in the 300 mm transition today. (For more on 300 mm, see article by Intel's Daniel Seligson). Because of the rapidity of developments in 300 mm technology, Semiconductor International will have a special 300 mm focus article in each issue throughout 1998.
