The Economics of 300 mm Processing

This short course in "Econ 300 mm" examines the costs associated with the transition to 300 mm wafers.

Daniel Seligson -- Semiconductor International, 1/1/1998

At A Glance The economics associated with the transition from 200 to 300 mm wafers are analyzed through the use of a DRAM wafer cost model and some simple tools, such as the "productivity plane." The costs associated with lithography, which is seen as both the largest contributor to capital cost and the tool set expected to have the least favorable scaling, are also highlighted.

The transition from 150 mm to 200 mm wafers promised a reduction of more than 20% in die cost but delivered less than 15%. It was a slow transition, taking more than five years from the first pilot line output to being in full swing. The first shortcoming contributed to the second, and the second to painful memories on the part of the equipment suppliers. IBM having borne the burden of the 200 mm transition and Intel having borne the 150 mm, we on the semiconductor manufacturers' side have painful memories of our own. With this history in mind, we set out in 1994 to work toward a 300 mm transition that would serve its stakeholders much better than the last. In this article, we discuss the economic aspects of this transition in progress and of the factors that we think are essential to its success.

The primary beneficiaries of a more productive 300 mm equipment set are the more aggressive DRAM manufacturers. They will use it to cut costs, reduce prices and gain market share in what can only be called a very challenging business. This will force a consolidation in that industry. In other segments of the semiconductor industry it will be a significant contributor to the fulfilling of Moore's prophesy, but only in DRAM will it make and break. For this reason, we will use a DRAM wafer cost model for most of the quantitative analysis shown here.

Of course, this is an oversimplification. Economics 300 mm is not merely about cost; it is about productivity in general. We define productivity to be "something" per unit output per unit time, specifying unit output per unit time in terms of wafer starts per week (wspw). Labor, factory floor space, pounds of emitted perfluorocompounds and capital investment can all be measured in these units and as such are measures of productivity, with factory floor space being a particulary important example. Moving into the 300 mm era, we have set targets for all the productivity measures and have put programs in place to meet those goals. While the transition to 200 mm may not have proved as cost effective as desired, it did increase our industry capacity. A 200 mm development facility in Santa Clara and a ramping 200 mm factory in Ireland provided Intel with great capacity in a market hungry for a new generation of microprocessors; Intel would not have been able to satisfy demand if its only option had been to build 150 mm factories.

The other beneficiaries are the semiconductor equipment manufacturers. These days they are seen as the bearers of the great weight of development. From another perspective they benefit from having a new product line to sell, one whose performance characteristics have been defined by international agreement among customers and one that will drive replacement in the suppliers' own installed base. It will, however, be a time of transition in the equipment industry with consolidation a likely outcome, depending on how suppliers respond to the standards and productivity imperatives.

Table 1. 0.25 µm DRAM Cost Model for 200 mm and 300 mm Wafers

Line item	200 mm		Scaling factor	300 mm
	$	%		$	%
Depreciation	793	41	1.50	1189	35
Labor	232	12	1.00	232	7
Maintenance	155	8	1.50	232	7
Consumables
Direct Materials	90	5	4.50	405	12
Test wafers	45	2	4.50	203	6
Indirect materials	445	23	2.00	890	26
Other	174	9	1.30	226	7
Totals	1934	100		3378	100
Equivalent				1407	73

Open standards

We believe that standards, particularly open standards, are essential to having a cost-effective and timely transition to 300 mm. Many of the standards center around data and material transfer interfaces, and we wholly support the Global Joint Guidance¹ document developed by I300I and J300. One hundred percent compliance to these interface standards is a must for all of our suppliers, because we cannot deliver wafers (manually or otherwise) to equipment unless the standards are implemented in every case. In production, compliance to these standards will bring improvements in capital, labor and factory floor space productivity; the final one coming with the advent of Overhead Vehicle delivery to process tools. Also, standard materials handling systems will be less expensive than custom ones, contributing to a further reduction in capital equipment cost. The design of the SEMI E15.1 loadport² permits use of a low-cost delivery system, which is not enabled at 200 mm. It is too soon for us to quantify these benefits, but our 200 mm experience tells us that they are positive.

The other area where standards are being used to cut costs and improve productivity is in tool evaluations. I300I has developed a set of testing procedures known as the Demonstration Test Methodology (DTM). The DTM cuts the cost of conversion by reducing redundant evaluations by multiple customers. Also, since the DTM is more stringent than the evaluations used by many in our industry, and the results are quite public to a large customer base, application of the DTM is forcing an overall increase of expectations for equipment performance; this can be seen by the average of 63 day slip of supplier commitments at I300I in 1997 as of this writing. As we are taught in management training, setting clear expectations is the first step in getting performance.

Finally, standards are driving costs down in the area of installation and gas box design. J300 has specified tool hookup configurations that if followed, would reduce installation time and enable prefabrication of components, further reducing costs. Similarly, SEMI is working toward a set of guidelines for "300 mm Process Tool Points of Connection to Facility Services," which is intended to accomplish much the same thing, but which would have international support.

Fig. 1. Using the model of Table 1, the depreciation scaling factor is treated as a parameter and varied over a wide range.

A 300 mm wafer cost model

We use a DRAM cost model (Table 1) to generate quantitative estimates of 300 mm wafer fabrication costs. The 200 mm 0.25 µm technology model shown here is based on cost category analyses from ISSM '94³, total wafer cost data from VLSI Research 1996 and widely available estimates of wafer cost and test wafer (or non-product wafer) usage. This is input. The output of this analysis is an approximate 300 mm 0.25 µm technology DRAM cost model. It is worthwhile to note that we try to eliminate ambiguity by not mixing together wafer size and technology transitions. As will be mentioned later, technology node transitions typically increase capital cost contributions to wafer cost. The benefits of wafer size transitions increase with increasing capital costs on the 200 mm side.

For each line item in Table 1 we show the model costs for 200 mm followed by the percentage that line item contributes to total wafer cost, and we identify Scaling Factors that incorporate our best knowledge about how the particular line item should scale in the transition.

For capital Depreciation, we assume that the process equipment is new and undepreciated. In the example illustrated in the table, we assume the scaling is 1.5, but we treat it as a parameter to be varied later; we call that parameter the Relative Capital Productivity. Implicitly, we assume equivalent technologies across the transition.

For Labor, we assert that the labor content per wafer should be the same for both wafer sizes, so the scaling factor is 1.0; actually, it should be less than 1.0 if the production lines become more fully automated.

Maintenance typically scales the same as depreciation.

Consumables includes silicon (direct materials) and test wafers, as well as indirect materials including spare parts, process gases, reticles and sputter targets. Direct materials and test wafer cost scaling is based on a mature double-side polished non-epi wafer cost of $405, a mean of estimates from several suppliers. This unfortunately large factor seems to be set by raw materials costs. Scaling for indirect materials is set at 2.0. We think the uncertainty in this factor is about 610%.

The last line item, Other, is line yield and various overheads, including factory facilities costs. These are forecast to have a cost scaling of about 1.3, based on estimates of tool size growth per wafer start and other factors.

The two right-hand columns are then the scaled costs for a 300 mm wafer and the recomputed percentages of total 300 mm cost. The last row in the table, labeled "Equivalent," normalizes the 300 mm wafer cost to that of a 200 mm wafer on a die out basis, giving both the absolute and percentage Equivalent cost. We will get 2.4, rather than 2.25, times the die out on a 300 mm wafer as compared to a 200 mm wafer because of packing density effects at the edge of the larger wafer; the factor 2.4 increases with increasing die size. Die yield and line yield are assumed to be independent of wafer size, given that both are 0.25 µm technologies. For more advanced technologies, the primary change is that depreciation increases in percentage terms, in-creasing the significance of its scaling factor. This model reflects industry norms at 0.25 µm for both DRAM and logic; Intel's more detailed 0.18 µm model gives essentially the same conclusions.

We define die cost reduction (in percent) to be 100 minus the percentage equivalent cost. In Figure 1, we show its dependence on the depreciation scaling factor, or relative capital productivity, varying it over a range from 1.1 to 2.0. Also, we show the results of a modified model in which the 200 mm wafer was manufactured on a line in which 50% of the equipment has been fully depreciated, a condition not unlike those under which we introduce new process technology today.

Relative capital productivity has the largest impact, although both silicon costs and indirect materials can have a large effect. The uncertainty in our estimates of silicon costs is small, so it introduces only about 1% uncertainty in the die cost reduction. The uncertainty in the scaling factor for indirect materials is large, introducing 3% uncertainty into the die cost reduction. Of the factors over which we have some control, relative capital productivity is the single largest contributor to die cost reduction. The very clear message of Figure 1 is that unless capital productivity scales at ~1.3, semiconductor manufacturers will be better served by upgrading existing facilities than by buying a new equipment set with its inherent risks.

Figure 2 shows a time series of die cost reduction estimates⁴ collected over the first 2.5 years of serious work on the 300 mm transition. Working backward from Figure 1, we infer that the authors of these estimates have concluded that relative capital productivity is going to be about 1.3.

Fig. 2. Data collected by Texas Instruments illustrate how forecasts on 300 mm productivity have trended over time.

The productivity plane

We attach great value to factory floor space productivity (factory cleanroom area/wafer starts per week), so in Intel's more detailed 300 mm cost model we explicitly consider its associated costs. We define the relative footprint, which is just the scaling factor for this term, and then we examine die cost reduction contours in the plane of relative capital cost and relative footprint. We call this plane the productivity plane. Figure 3 is such a graph, and in it we indicate our target die cost reduction as the solid red line. The target is the value (of die cost reduction) that justifies taking the risk to make the transition. The direction normal to the contours indicated by the arrow pointing down and to the left is the direction of increasing producitivity; movement in that direction results in greater die cost reduction.

In order to meet our targets, the relative capital productivity and relative footprint (hereafter called capital and footprint, respectively) need to fall below the red line; the further below the better. Since the target line goes through the point capital = 1.3, footprint = 1.0, we have used this conveniently stated fact to specify our requirements to the industry. In the simplest language, for a given number of 200 mm and 300 mm wafer starts, 300 mm tool costs should not be more than 30% greater than their 200 mm counterparts, and the factory space required should be the same or less. This seems to be consistent with estimates in Figure 2.⁵

The productivity plane is a useful tool for comparing performance of individual tools, as well as of the tool set as a whole. We routinely use it as a means of comparing candidates in our 300 mm equipment selections, and have asked suppliers to present data on their tools to us in this fashion. Since 1995, we have monitored the trajectory of the estimated performance of the tool set in the direction of increasing productivity. Figure 4 is an example of how we use the productivity plane to examine the performance for individual tools in the equipment set. Data from each supplier and from each tool set are plotted; the mark area being proportional to a tool set's estimated contribution to overall capital expenditures. Open marks are for exposure tools and tracks. We are quickly able to identify tools for which scaling is unattractive, and we put programs in place to address the problem tools. The early data shown here produce overall productivity factors of capital = 1.8 and footprint = 1.4, well above current estimates.

We build up estimates of the overall scaling factors using a fab capacity model that accounts for the performance of individual tools. Contrary to reports by VLSI Research,⁶ which say that capital cost premium will be between 50% and 100%, data collected from suppliers tell us that suppliers will meet our productivity targets.

In the financial community, productivity factors are a proxy for average selling price of tools. There seems to be concern that if the productivity factors are too favorable, the suppliers will suffer, along with their profits and stock prices. We believe otherwise. A highly productive tool set will drive rapid replacement of the 200 mm installed base and rapid return on investments suppliers have made. The acceleration of announcements from DRAM manufacturers for pilot activities in 1998 corroborates this viewpoint. Of course, competition will determine prices and ultimately productivity. A strong, diversified base of capital equipment suppliers helps assure us of getting the needed productivity. A plausible time-to-money model illustrating dependence on parameters such as those described here would answer the question of whether there is a lower bound on capital and footprint that makes the transition unattractive from the suppliers point of view.

Fig. 3. Two measures of capital equipment productivity are considered as independent dimensions: the scaling factors for capital and for tool size.

Lithography

Lithography, including exposure tools and resist tracks, is both the largest contributor to capital cost and the tool set expected to have the least favorable scaling. Lithography costs continue to escalate, and today they are typically 30-40% of overall capital in a 0.25 µm technology. Exposure is the most difficult from a standpoint of scaling because it is an area-based process, not a wafer-based one. The tracks, while not area-based, will have their productivity dragged down by the slower exposure tools. The advent of 9 in. reticles should provide a runrate improvement of about 10-20%.⁷ With this included, we are anticipating that the scaling factor for lithography tools, exposure and track combined will be well below 1.7.

It is useful to examine the sensitivity of die cost reduction to lithography tool costs. Figure 5 shows such an analysis for the DRAM cost model above. Over a wide range of non-litho capital (1.3-1.6), lithography costs as a fraction of total capital (30-50%) and litho capital (1.3-1.7), die cost reduction is relatively constant at 28.5% ±3.5%. As lithography costs increase as a fraction of total cost, as they are likely to do in more advanced technologies, the die cost reduction increases.

Nine inch reticles are coming, but with a price tag higher than the 6 in. reticles they are replacing. The 10-20% lithography productivity improvement buys about 2% die cost reduction. The added indirect materials cost of 9 in. reticles must not offset that productivity gain. A reasonable target for the 9 in. reticle cost adder is that it be <1/10th of the 2% die cost reduction. For a 20 mask layer DRAM technology in which reticles get an average of 20,000 exposures each, this implies that the adder be <$6600 per reticle. This is about fivefold lower than industry estimates of the adder. Within the context of this model, it does not look like 9 in. reticles are going to pay for themselves. However, there may be other reasons to drive for 9 in. reticles. These include the fact that there is a persistent worldwide shortage of exposure tools, so reducing demand by 15% may be desirable; the extra 4% or so of factory capacity gained by a 15% increase in exposure tool productivity; and the operational benefits associated with having 15% fewer exposure tools. The debate on the merits and realizable potential of 9 in. reticles will continue to rage for some time.

Fig. 4. The productivity plane is useful for comparing the performance of individual tools.

Transition costs

Another often discussed aspect of this transition is how much it will cost. In 1996, Dataquest⁸ published an estimate of the initial investment costs of equipment, silicon and semiconductor manufacturers, arriving at the figure of $20B.^* Our take on the initial industry investment cost provides a quite different estimate of the investment, as ours takes into account the investment cost of 200 mm capacity that we would have built had we not built the new 300 mm capacity.

We define the transition to be complete when N companies have built and operated pilot lines and have built high-volume factories. Assume the following: a pilot line has a capacity of 1200 wspw and a factory has 5000 wspw. A new pilot line costs less than $1B to build and operate over its two- to three-year lifetime before being released to manufacturing. A 5000 wspw 300 mm factory costs $1.6B to build, if capital=1.5 and footprint=1.2. Combined, this pilot line and factory can produce 15,000 wspw of 200 mm equivalents. A 200 mm factory producing 7500 wspw costs $1.7B. Tallying investment on the equipment side, suppliers will develop T tools, each costing less than $40M on average. If there are T=150 tools developed, and N=10 semiconductor manufacturers following this scenario, the industry investment cost of conversion is negative:

10*($1.6B - 2*$1.7B + $1.0B) + 150*$0.04B =
-$2B

The result is quite insensitive to the choice of numbers. In other words, the initial industry investment for 300 mm is equivalent to or even slightly favorable relative to the cost of building a comparable quantity of 200 mm capacity. The key is to account for the fact that the semiconductor manufacturers are making investments they would have to make even without conversion to 300 mm.

There are some other costs to account for, like the cost to develop 300 mm silicon, but these are relatively small compared to the costs considered here. Even varying the factory cost assumptions substantially, little change is made to the conclusion that the cost of conversion does not approach $20B.

As for the time to recover investments, it depends on many factors outside the scope of this article. If the Die Cost Reduction is attractive, the conversion time will be about one half that of the 200 mm transition, with prompt return on investment for the capital equipment suppliers.

Fig. 5. Lithography is the single largest contributor to capital depreciation.

Conclusion

Unlike the transition to 200 mm, the transition to 300 mm is following in the wake of a series of internationally adopted standards and accepted productivity goals. Across the industry, we are using simple tools such as the productivity plane to track performance estimates against 200 mm productivity. Independent estimates of the expected die cost reduction exceed 25% and are backed up by detailed fab capacity analyses and wafer cost models. Lithography exposure costs are expected to be high, but their increasing costs make 300 mm even more attractive, although their overall influence is only a few percent over the expected range of variation. Based on interviews with many suppliers, analysts and semiconductor manufacturers, we expect the first pilot lines to be producing integrated silicon in late 1999 and the first production lines to be operating and ramping within 18 months. The 300 mm industry transition will be in full swing in 2001, one-half the time it took in the last transition.

Acknowledgments

The thoughts, models and figures going into this article summarize more than three years of work. I want to express my thanks to Paolo Gargini, Janice Golda, Gulsher Grewal, Bob Jecmen, Don Rose, Peter Silverman and John Souza for their many tangible and intangible contributions to this work.

References

1. Global Joint Guidance for 300 mm Semiconductor Factories, July 1997

2. Semiconductor Equipment and Materials International

3. Jack Saltich, ISSM '94

4. Robert Doering, Semiconductor International 1997

5. The author of Figure 1 was not privy to our estimates of Die Cost Reduction.

6. VLSI Research 1997 note on 50% to 100%

7. For those semiconductor manufacturers whose products are constrained by today's scanner field sizes, 9 in. reticles will have an additional impact not captured by this productivity measure.

8. Clark Fuhs, Dataquest, 1994

^*Quite obviously, over a period of a few years, there is a positive return on the investment, so the net present cost of the investment is negative, i.e., favorable.

Daniel Seligson is manager of 300 mm programs for Intel Corp's Process Equipment Development Group. In 1994 and 1995, he was Intel's representative to the SEMATECH Large Wafer Task Force, which ultimately spun off as I300I. Seligson has also managed equipment programs in implant, thermal processing and electroplating. E-mail: daniel_seligson@ccm.sc.intel.com

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