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Process Manufactures High-Volume, Low-Cost HDI Substrates

Eric Bogatin, Contributing Editor -- Semiconductor International, 8/1/2001

Pop quiz: What product is produced at nearly 1 billion ft2/year, with precision-located 1 µm holes over a 6 in. field, at a cost of pennies per square foot? For extra credit, what's the manufacturing process?

Answer: It's not silicon wafers, which can cost more than $10k/ft2, and it's not printed circuit boards (PCBs), which can cost more than $100/ft2. It's laser and compact disks (CDs).

The manufacturing process is embossing or imprinting, which uses a master fabricated with a precision array of small, blind holes using advanced photolithography. Then a "stamper" is made by standard nickel electroforming. The stamper is pressed against a CD blank at elevated temperature and the electroformed bumps replicate depressions in the blank. Millions of CDs can be stamped out from one tool at pennies a copy.

This same low-cost, high-volume, precision embossing technology could change how microvia-based PCBs are manufactured — if George Gregoire, founder and president of Dimensional Circuits (San Diego), has his way.

Dimensional Circuits was founded in 1990 as an R&D organization to further develop the emerging technology of imprint patterning for microelectronics applications. "We've taken a systems approach to the fabrication of advanced circuits in trying to cut out a lot of the steps of conventional technologies," Gregoire said.

The process for fabricating a fine-line, microvia substrate involves embossing a pattern of grooves and holes in a blank substrate. The traces are formed at the same time as the holes. The depressions are coated or filled with conductive material. In a multi-layer structure, subsequent layers of embossable material are applied over the previous layers, and imprinted again. Holes that make contact with the underlying conductor provide the basis for multi-layer connections.

In one version, tested in collaboration with Ormet Corp. and Dexter-Loctite, the conductors are thick-film conductive inks squeegeed into embossed grooves and holes. In another version, the imprinted features are blanket metallized using electroless and then electroplated copper. A resist is squeegeed into the grooves and holes with no registration or imaging step required. The exposed copper not in the grooves is etched away. Metallized traces and via holes remain after the etch resist is stripped off. In both cases, imprint patterning provides the lithography to define the fine lines and vias. Prototypes have been fabricated with 50 µm lines and spaces and with 50 µm vias to underlying layers.


The illustration on the right shows the manufacturing process: After the substrate is embossed with the traces and vias, the surface is blanket metallized. Resist is squeegeed into the grooves and the exposed metal is etched off. A single layer of embossed interconnect can be applied to a conventional board to provide fine features (left). (Source: Dimensional Circuits)

Imprint technology has been demonstrated for much finer features. In the last two years, sub-100 nm features have been embossed at the Texas Materials Institute (University of Texas, Austin), and at Princeton University's Nanostructure Lab.

Both thermoplastic and thermoset materials have been used for the dielectric layers. "Quite a wide range of materials, such as epoxies, polyimides and liquid crystal polymers, have been used — even ceramic greentape," Gregoire said. "It's just important to avoid long fibers when forming microvias, and thermoplastic materials imprint the fastest."

Conductors and vias are patterned at the same time with the same embossing tool-foil. This means truly padless microvias are possible, at least on both outer layers. There is still the registration issue between layers.

This technology may offer extremely low-cost manufacturing, as imprinting skips many of the processing steps of conventional HDI. In addition, it requires no new capital equipment because imprinting can be done in an ordinary laminating press.

Though still just an emerging technology, Gregoire has targeted the technique at low-cost IC package substrates as a likely initial application. A two-layer substrate can provide extremely high-density interconnect at low cost. As the technology moves up the learning curve, imprint patterning could be applied to the complete spectrum of HDI boards, from small packages and rf modules to large back planes with many layers.

For additional information on assembly and packaging, go to www.semiconductor.net/assembly


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