Single-Wafer Cleaning vs. Batch Cleaning
Maria A. Lester, Associate Editor -- Semiconductor International, 8/1/2001
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At the recent SCP Global Technologies 8th International Symposium, researchers from Agere Systems (Orlando, Fla.) discussed the future prospects of single-wafer cleaning where improved process cleaning is eminent to single-process insertion. Potential process improvements were shown in linewidth loss.
The results shown in Table 1 indicate that CD linewidth loss can be eliminated with single-wafer processing. Another improvement was that rising efficiency could be augmented using single-wafer cleaning. A single-wafer cleaning system was shown to have improved surface roughness.
What is it that is holding single-wafer processing back? The main issues are low throughput and high cost. Table 2 compares the cycle time of single-wafer processing with wet bench processing, and shows that, for single-wafer processing a total time of 4 min results in a 15 wph throughput per chamber. Therefore, a four-chamber system would achieve 60 wph throughput and an eight-chamber system, 120 wph.
| Table 1. Electrical CD Linewidth Loss | ||
| Isolated linewidth loss | Nested linewidth loss | |
| Batch solvent | 130 Å | 290 Å |
| Single-wafer solvent | 0 Å | 150 Å |
| (Source: Agere) | ||
| Table 2. Cycle Time Comparison | ||
| Process step | Single-wafer | Wet bench |
| HF | 30 sec | 120 sec |
| Rinse | 30 sec | 600 sec |
| SC1 | 30 sec | 600 sec |
| Rinse | 30 sec | 600 sec |
| SC2 | 30 sec | 600 sec |
| Rinse | 30 sec | 600 sec |
| Dry | 60 sec | 600 sec |
| Total time | 4 min | 62 min |
| (Source: Agere) | ||
Two-Step Cleaning Concept for Metallic Surfaces
Researchers from STMicroelectronics (Agrate, Italy) and Tohoku University's Department of Electrical Engineering (Sendai, Japan) recently presented a new two-step wet clean for metallic/oxide surfaces at the SCP Global Technologies 8th International Symposium.
This wet treatment concept is based on the combination of an HF or HF/H2O2 etch and the control of the Zeta potential value using a surfactant followed by an ozonated DIW rinse. The researchers suggested it could be a candidate for more than 70% of the cleanings in future device manufacturing.
They proposed using HF concentration to control the oxide etch rate and adding surfactant to decrease the residual particle count. The presence of the surfactant along with a tight control of the etched thickness can provide a particle-free surface with no residues. Therefore, a small amount of two precisely controlled chemicals may dispose of standard chemicals for all metal-involved cleaning.
Advantages to the two-step clean include the use of only two chemicals for all the materials, easily controlled ER of the metals, no tiny pattern lift-off (no megasonics used), no significant oxide etch and no residues.
For additional information on clean processing, go to www.semiconductor.net/clean
