Controlling Plasma- and Process- Induced Damage

		At a Glance
	This report from the 6th International Symposium on Plasma- and Process-Induced Damage (P2ID) reviews recent work and provides a prognosis for the future directions of research.

Although many of the problems and mechanisms involved with process-induced damage have yielded to the attention of the industrial and academic research communities over the past several years, some items still remain unresolved, and new materials and processes also are evidencing new phenomena.

At the 6th International Symposium on Plasma- and Process-Induced Damage (P2ID), held in May in Monterey, Calif., the latest progress on these issues was reported. Some of the new issues facing the industry include the consequences of the introduction of new technologies such as copper, high-k and low-k dielectrics, and the emergence of the importance of multiple-terminal devices coupled with the failure of the simple gate-antenna model of charging damage.

Back-end-of-line processes

Charging-related damage is probably most often associated with back-end-of-line (BEOL) processing. Profound change in the BEOL structure is spreading, as the industry moves from subtractive etch Al wires in oxide insulators to damascene Cu wires in oxide (sometimes fluorinated) or low-k dielectrics, as shown in Figure 1. Researchers from IMEC compared the nature and degree of damage in their implementation of these two schemes and detailed the different processes that contribute to damage in each case.¹

The damage at contact and via level was found to depend strongly on the design of the overlaying metal, because the width of that line modifies the aspect ratio during the etch and hence contributes to electron shading. Although the deposition of the low-k insulator by spin-on did not contribute any damage, the sputtering of the barrier film into the via was shown to cause charging, exacerbated in the case of the "bottomless" via.

Another aspect of BEOL processing was illustrated in work by CEA-LETI,² in which the bow introduced into the via profile in soft low-k dielectrics such as SiLK during etch was shown to be caused by electron shading and the accompanying ion trajectory distortion.

Gate insulators

The reaction of thin gate dielectrics to charging damage continues to be of interest. Data was presented that showed a distinction between devices exhibiting soft breakdown and those that showed only hard breakdown.³ The devices with soft breakdown showed a significant antenna effect, i.e., devices with larger metal antennas showing a greater leakage. In contrast, hard breakdown occurred at the same rate for all devices, regardless of antenna ratio.

Researchers from Philips also concluded that soft, rather than hard, breakdown is associated with plasma charging damage, and pointed out that soft-breakdown leakage is unlikely to cause circuit malfunction, although the long-term reliability is adversely impacted.⁴

In other work, the issue of product yield was addressed through the development of a model of failing fraction as a function of antenna ratio, followed by application of that model to the antennas found in the product.⁵ However, it is necessary to assume that gate leakage induces circuit failure.

New constituents such as high-k insulators and the isotope deuterium made their appearance as well. Provided that one can introduce and retain it in the gate dielectrics, deuterium offers improved hot-carrier immunity and also may provide additional resilience with respect to breakdown.⁶

Despite the fact that severe limitations for silicon dioxide-based gate dielectrics may be seen in the next three to five years (or less), research in high-k insulators as a replacement is still relatively immature, with many different films still vying for primacy.⁷ Using these films introduces the added complexity of elements such as Zr and Hf, heretofore absent from silicon semiconductor processing, with the concomitant potential for undesired contamination.⁸

Multi-terminal effects

Conventional antenna rules specify the maximum size of the charge-collecting node attached to the gate node. Some of the work reported here clarifies how the other terminals of the device (the source, the drain and the bulk) contribute to the damage inflicted on the device.

Silicon-on-insulator (SOI) devices are particularly immune to charging damage because the potential across the oxide is established by the gate antenna relative to the antennas on the source and drain, as the body is not constrained to be at the bulk potential.⁹ Differential antenna effects may be observed in SOI, but only for differences in kind, not in size.

Figure 2 illustrates some of the possible current paths in bulk and SOI technologies. In bulk technology (a), current collected on the gate node may return to the plasma through source/drain contacts, through the substrate contacts or through the wafer back side to the chamber and hence to the plasma. In SOI technology (b) the return current path through the bulk silicon is not available because it is interrupted by the buried oxide.

Other work supports the notion that damage is minimized if the bulk potential is established by the plasma from the top of the wafer. It was shown that devices with grounded sources were more susceptible to damage.¹⁰ The response of CHARM-2 test devices was minimized by increasing the number of connections from the top of the wafer to the substrate,¹¹ and a model incorporating leakage from the substrate to the wafer chuck was used to explain the reduction of charging damage with the addition of back-side oxide.¹²

These reports emphasize that a complex combination of current paths sets the potential of the wafer bulk: leakage to the wafer chuck, antennas to the substrate, antennas to the source/drain nodes and junction leakage. Careful attention to the other antennas involved in charging will lead to a better understanding of how the potential difference develops across the device and damages it.

Conclusions and prognosis

As for the future, advances in semiconductors will produce new and different challenges to controlling damage. New methods of integration and new materials will continue to be a focus of research as low- and high-k films make further inroads into mainstream production.

Further investigation on control of the substrate potential will be important in reconciling apparently disparate empirical results, and developing more effective design rules. These and other aspects of process-induced damage, such as physical disruption and particulate contamination, will continue to be vital in reducing the adverse impact of using plasma processes. Ongoing efforts to meet these challenges will be the focus of future P2ID meetings. P2ID'02 will be held in June in Maui, Hawaii, just before the VLSI Symposium. Details and the call for papers have been posted at www.p2id.org.

Terence Hook is a senior technical staff member at the Semiconductor Research and Development Center at IBM Microelectronics. He received his Sc.B. from Brown University and Ph.D. in electrical engineering from Yale University. He has worked on technology integration and device design for bipolar, BiCMOS and CMOS technologies, and more recently, process-induced charging issues. He is the general chair of the 2002 P2ID conference.

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REFERENCES

1. G. Van den Bosch, D. De Jaeger, Z. Tokei, G. Groesenecken, "Plasma Charging Damage Issues in Copper Single and Dual Damascene, Oxide and Low-k Dielectric Interconnect," Proc. 6th International Symp. on Process- and Plasma-Induced Damage, Monterey, Calif., 2001, p. 8.
   
2. O. Joubert, L. Vallier, J. Foucher, D. Fuard, G. Cunge, "Fundamental Limitations in the Design of Front End and Back End Plasma Etch Processes," Proc. 6th International Symp. on Process- and Plasma-Induced Damage, p. 2.
   
3. G. Cellere, M. Valentini, A. Paccagnella, "Correlation Between Soft Breakdown and Plasma Process-Induced Damage," Proc. 6th International Symp. on Process- and Plasma-Induced Damage, p. 40.
   
4. A. Scarpa, L. van Marwijk, W. Peters, D. Boter, F.G. Kuper, "Yield and Reliability Effects of Interlevel Dielectric Plasma Enhanced Deposition Induced Charging Damage," Proc. 6th International Symp. on Process- and Plasma-Induced Damage, p. 44.
   
5. Z. Wang, A. Scarpa, C. Salm, F. Kuper, "Relation Between Plasma Process-Induced Oxide Failure Fraction and Antenna Ratio," Proc. 6th International Symp. on Process- and Plasma-Induced Damage, p. 16.
   
6. W. Clark, E. Cartier, E. Wu, "Hot Carrier Lifetime and Dielectric Breakdown in MOSFETs Processed with Deuterium," Proc. 6th International Symp. on Process- and Plasma-Induced Damage, p. 80.
   
7. J. Suehle, et al, "Challenges of High-k Dielectrics for Future MOS Devices," Proc. 6th International Symp. on Process- and Plasma-Induced Damage, p. 90.
   
8. W. Pamler, "New Elements in Si Technology — A Contamination Risk?" Proc. 6th International Symp. on Process- and Plasma-Induced Damage, p. 94.
   
9. A. Mocuta, et al, "Plasma Charging Damage in SOI Technology," Proc. 6th International Symp. on Process- and Plasma-Induced Damage, p. 104.
   
10. W. Lin, G. Sery, "Role of Source/Drain Junction on Plasma-Induced Gate Charging Damage in N MOSFET," Proc. 6th International Symp. on Process- and Plasma-Induced Damage, p. 112.
    
11. W. Lukaszek, C. Gabriel, "The Effect of Substrate Connections on Charging Potentials and Current Densities," Proc. 6th International Symp. on Process- and Plasma-Induced Damage, p. 116.
    
12. N. Mise, et al, "A New Current-Balance Model for Predicting Charging Damage During High-Temperature Plasma Processing," Proc. 6th International Symp. on Process- and Plasma-Induced Damage, p. 108.
    

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