SI CHINA     SI JAPAN
Login  |  Register          Free Newsletter Subscription
Subscribe
Email
Print
Reprint
Learn RSS

From Motorola's MOS10 to Tower

Jeff West, Motorola Semiconductor Products Sector, Austin, Texas. Erez Imberman, Tower Semiconductor Ltd., Migdal Haemek, Israel -- Semiconductor International, 8/1/2001

At a Glance

A case study of process transfer from an integrated device manufacturer to a wafer foundry.

This paper reports on the approach used to successfully transfer two submicron, mixed-signal IC processes (six unique devices) from MOS10, Motorola's former 150 mm fab in Irvine, Calif., to Tower Semiconductor's fab in Migdal Haemek, Israel. The unique and challenging conditions described here provide insight into the operations and techniques for successfully transferring processes from an integrated device manufacturer (IDM) to a foundry partner in a compressed timeframe.

Project goals and milestones

  • To qualify TS80 and TS60 double poly, double and triple metal process flows at Tower.
  • To meet or exceed MOS10's yields in Tower.
  • To transfer all required products from MOS10 to Tower by October 1998.
  • To meet or exceed all customer requirements now satisfied by MOS10 die with die manufactured by Tower.

Backdrop

Before the transfer began, a rare set of events had unfolded that turned a difficult process transfer into one with little or no margin for error, as well as one with much less time to accomplish than either company had been given before.


1.
Engineers had only 8.5 months to complete the transfer.

Motorola had already announced it was closing MOS10 in a move to consolidate and streamline its wafer manufacturing capacity in an effort to improve long-term return on assets. The initial date for closing MOS10 was set for Jan. 1, 1999, but it was accelerated to Oct. 31, 1998. The transfer was officially kicked off Jan. 25,1998, in the first face-to-face meeting between MOS10 and Tower engineers and project managers. But product groups controlling the necessary engineering resources were not available until mid-February, only 8.5 months before the fab was set to close. A detailed project plan for the transfer is shown in Figure 1.

Process transfers are usually undertaken to free up capacity in a more expensive fab. Delays due to qualification failures or fab-to-fab incompatibilities are manageable because the source fab can be relied upon to supply wafers in an emergency. In this case, however, MOS10 was to be permanently closed on Oct. 31, 1998. The MOS10 employee redeployment schedule was based on this date. Equipment was decommissioned and shipped to other Motorola fabs based on this date. There was no capability for providing emergency supply from MOS10 in case of transfer problems in Tower because the last wafer start was to be Sept. 1, 1998. As finally scheduled, there were only three months between this date and the time the last device transfer was to begin. In contrast, process transfers within an organization from one fab to another can take up to a year, and this often benefits from the fact that the equipment mix is identical or highly compatible (Fig. 2).


2. While most transfers take much longer than planned, the Tower transfer had to be completed on time and in a compressed timeframe.

IC process technology transfers are notoriously difficult because equipment sets rarely match, and a slight difference in any of the 120 or so process steps can be a source of failure. This is particularly true for mixed-signal circuits whose analog components are especially sensitive to the most minute process differences. Before the MOS10-Tower transfer, the speed record for completing a multi-device, mixed-signal transfer at Motorola was just over one year. Historically, more than one cycle of learning is required to get the process driver yielding at a high enough rate to generate enough confidence in the product engineering community to transfer additional devices running on the same process. Invariably, yields on one or more of the subsequent devices would come up quickly, generating a false sense of security. And, just as consistently, one or maybe two of the more process-sensitive devices would initially yield "0" or close to it, taking weeks of engineering time to debug before the next round of silicon could be started. Each learning cycle could take from six to eight weeks, including wafer processing, shipping for probe, isolating and, finally, making the change that would fix the problem.

Most IC product/process transfers are constrained by time to minimize cost, either engineering time and/or risk in terms of interrupted supply to the end customer. This latter risk can be addressed by building inventory in the source fab, but this, too, adds to product cost. Based on prior process transfers, it was decided to build inventory for each product that would last one year from the time the transfer was begun at existing run rates or demand levels. Experience had shown that an individual process/product transfer would take from six months to one year, including process, product and customer qualification periods. Therefore, inventory had to be built to cover the estimated transfer period plus time for two or three learning cycles. Figure 3 shows the best-case scenario, assuming no delays and no resource constraints.


3. The best-case scenario, assuming no delays and no resource constraints.

Given the time constraints, there was insufficient time to do a "copy-exact" transfer, where every process and device parameter in the source fab is matched in the receiving fab.

"Flying wafers" methodology

Several early lots of the first process driver were processed in a unique way. The first block of the first module — the well module (other modules include isolation, the transistor and interconnects) — was processed in MOS10. Subsequent modules were processed alternatively between Tower and MOS10. This enabled the team to isolate sources of yield loss and parametric differences to individual modules or blocks, radically reducing troubleshooting time. Two lots were processed exclusively in MOS10 to provide a baseline for the experiment. All photolithography had to be done in MOS10 because Tower steppers/alignment marks were different.

Qualification

Two devices were used to qualify the two processes: a two-way radio controller for the 0.8 µm process and an ISDN transceiver for the 0.65 µm process. The global standard JDEC test battery was performed, including 1008 hr at elevated temperatures (HTOL, high temperature operating life), ESD, latch-up, temperature cycling, preconditioning, autoclave and HAST. Once the process was qualified, subsequent products were only required to pass preconditioning, ESD, latch-up and an abbreviated HTOL test (96 hr). Some product groups elected to extend the HTOL test duration beyond the required time to determine the lifetime of individual products, providing valuable information to Tower on elevated temperature failure modes.

All devices passed all tests except ESD. Failures were due to an outdated ESD device design that passed the human body model but not the machine model executed after the device was first implemented. The product groups agreed that ESD failure rates less than or equal to those incurred at the MOS10 qual would be acceptable.

The soft factors

There is often an obvious focus on the engineering or technical hard factors that have enabled a successful transition. However, much of the success in this case study can be drawn from what can be described as the soft factors — the engineering teams involved in the project. A key element was the term "trust." All team members, whether from MOS10, Tower, product groups or manufacturing, openly shared data and mistakes (and successes). Problems were never personalized; people always stayed focused on the issues.

Another soft factor was the ability to establish and maintain a real-time feedback loop. This entailed real teamwork: Constant phone and e-mail communications, clear assignment of responsibility, attention to detail, expert data organization, and the team's high level of involvement enabled problems to be identified quickly and resolved without finger-pointing or bureaucratic machinations. The ability to maintain a closed loop throughout the project was dependent on motivation.

Leveraging time differences

The demands of time-compressed technology transfers do not conveniently fit into 8 a.m.-6 p.m. time periods, and everyone on the team accepted that fact. There were plenty of exciting things that occurred during the worst times and required engineering attention. Flexible work schedules for the engineers and project managers enabled problems to be attacked as soon as the data was available, rather than the following morning.

The team also exploited the time difference between Tower and MOS10. MOS10's workday began just as Tower's workday ended, so there was only a 4 hr gap each workday when one of the two first-shift engineering teams in Israel or California was not available to work on the transfer. The daily conference call was held at the end of Tower's day (beginning of MOS10's); MOS10's reactions to the call's action items would arrive at Tower just before Tower began its next day. Likewise, new data out of Tower would arrive at MOS10 just as MOS10's day began. The different work weeks were also exploited. Tower's week begins on Sunday rather than Monday in the United States; therefore, with the time change, the normal 2.5-day gap was reduced to 30 hr.

Time was more precious than money, and both Tower and Motorola leadership teams recognized that fact early on and staffed the transfer with the best talent. While project managers on both sides watched expenditures carefully, money was spent to reduce cycle time or risk.

Lessons learned/weak links

The weakest link in the transfer was mask prep. The errors ran the gamut from corrupt databases to layout errors to mask generation errors. A valuable procedure implemented to minimize the time delay caused by errors was to compare fractured data. An XOR was performed between the original data and the data after Tower's addition of test structures and alignment keys. Reviewing the polygons for each level allowed us to detect missing data in two instances, saving the cost of two flawed reticles and a month of wasted wafer processing and debug time.

Conclusion

From the outset the challenges were clear: Move two mixed-signal process flows from California to Israel in eight months with no interruption in the supply. Success was enabled by support at the top of both companies; a well-organized effort from two highly skilled engineering teams; and excellent daily (sometimes hourly) communications.

In addition, intense time pressure and the importance of the project raised and maintained the intensity level, kept the team focused on rapid problem-solving and institutionalized open-mindedness in solving those problems. The mask-making process was the most problematic, but reviewing a comparison of fractured data minimized delays.

Jeff West is foundry engineering manager at Motorola's Worldwide External Technology group, where he is in charge of Motorola's foundry business in Tower Semiconductor. Previously, he held positions in process development and integration in Motorola's advanced CMOS R&D group. He has an MSEE degree from the University of New Mexico, an MSIA from Purdue University and a B.A. from Southern Methodist University.
E-mail: jeff.west@motorola.com

Erez Imberman is manufacturing manager at Tower Semiconductor Ltd. Previously, he was project manager in R&D, where he dealt with development of methodologies for technology transfer from development to manufacturing. He has a B.A. in statistics and political science from Haifa University and an MBA from Heriot-Watt University.
E-mail: erezi@towersemi.com


Email
Print
Reprint
Learn RSS

Talkback

We would love your feedback!

Post a comment

» VIEW ALL TALKBACK THREADS

Related Content

Related Content

 

By This Author

There are no other articles written by this author.

SPONSORED LINKS



 
Advertisement
SPONSORED LINKS

More Content

  • Blogs
  • Podcasts
  • Videos

Blogs


Sorry, no blogs are active for this topic.

» VIEW ALL BLOGS RSS

Podcasts

Videos

Advertisements





NEWSLETTERS
Plug in and get the latest SI news, trends and industry updates delivered free, directly to your inbox!

SI NewsBreak and Special Reports (Weekdays)
Wafer Processing Report (Monthly)
Lithography Report (Monthly)
Metrology Report (Monthly)
Clean Processing Report (Monthly)
Packaging Report (Twice Monthly)
©2008 Reed Business Information, a division of Reed Elsevier Inc. All rights reserved.
Use of this Web site is subject to its Terms of Use | Privacy Policy
Please visit these other Reed Business sites