Process Metrology for Ultrathin Gate Dielectrics

David Leet, Daewon Kwon, George Collins, Jana Clerico Rudolph Technologies, Flanders, N.J. -- Semiconductor International, 8/1/2001

At a Glance
A novel method is presented that is able to measure ultrathin gate oxides under a thick layer of polysilicon with better than 0.005 nm repeatability. This method also measures polysilicon thickness, its amorphous/crystalline volume fraction, and the combination of polysilicon roughness, native oxide and MAC adsorption on the wafer surface.

In the continuing quest to produce smaller, faster, lower-power semiconductor devices, transistor gate thicknesses have been shrinking at an increasing rate.¹ Virtually all semiconductor manufacturers today are striving to reduce gate oxide thickness to below 2.5 nm. According to the 2000 update of the International Technology Roadmap for Semiconductors (ITRS), the trend is clear — the target equivalent oxide thickness for a gate dielectric stands at 1.5-1.9 nm this year and is forecast to shrink to 1.0-1.5 nm by 2005, with process thickness control of ±4% (3 s).²

Achieving high-volume production of stable ultrathin silicon dioxide (SiO₂) gate films has become very difficult. This is partially due to the traditional processing sequence in which the gate oxide is grown in an oxidation furnace and the polysilicon gate electrode is subsequently deposited in a separate processing tool. Between gate oxide formation and polysilicon deposition, the gate oxide is exposed to the fab environment, allowing adsorption of molecular airborne contaminants (MACs). These contaminants have been shown to have a negative effect on gate oxide integrity, and they are known to cause the measured thickness of the gate oxide to increase over time.³

Newer production methods form both the gate oxide and the polysilicon sequentially in the single vacuum environment of a cluster tool, speeding the polysilicon/gate oxide film-stack formation process and avoiding the opportunity for MACs between the two layers. Accurately and repeatably measuring the thickness and uniformity of ultrathin gate oxides under a thick layer of polysilicon, which also develops an adsorbed layer of MACs on its top surface, is a very challenging multi-parameter metrology problem.

 

Process control requirements

Precisely controlling the thickness of ultrathin SiO₂ gate dielectric films is critical for high-yield, advanced-generation semiconductor manufacturing. Thinner gates enable faster transistors that consume less power, but weak spots or defects in the film can result in the electrical breakdown of the dielectric and failure of the transistor. The film must be thick enough to prevent large gate leakage currents caused by direct quantum mechanical tunneling and to prevent device instability caused by boron penetration into the underlying gate channels.⁴ With SiO₂ gates in the 1.5-2.0 nm range, the ITRS requirement for measurement repeatability is 0.006-0.008 nm and, by 2005, the repeatability requirement is projected to be 0.005 nm.²

1. One film stack was used to measure all four critical parameters of the polysilicon/gate oxide film stack: the gate oxide, polysilicon, and TopOx thicknesses and the polysilicon V f (a). To check the model, the sample was compared with a single-layer gate oxide stored in the same location (b). The rate of adsorption of MACs on the single-layer gate oxide and the top native oxide of (a) both show a growth rate of ~0.05 nm over the seven-day period.

There are at least two possible reasons for the previously mentioned increase in measured thickness of ultrathin gate dielectric films. The first is actual growth of the SiO₂ layer over time as a result of oxygen diffusion into the silicon. This growth can be significant when a layer of native oxide is forming on the surface of bare silicon (or polysilicon), but is not a major factor when thermally grown gate oxide thickness exceeds the 1-1.2 nm diffusion-limited thickness of a typical native oxide film. Native oxides have been shown to stabilize at this thickness within a few hours.⁵ The second mechanism that can cause the measured thickness of an ultrathin oxide film to increase over time is the adsorption of a layer of MACs on the surface of the SiO₂ film.

These adsorbed contaminants appear to be organic compounds because they can be removed by rinsing with an oxidizing agent.⁵ While cleanroom air may be particulate-free, it can have higher levels of molecular organic contaminants than office environments because of volatile process chemicals used in the fab, and because of the more frequent air circulation through organic filter media that is used to trap particulates.⁶

One way to achieve more repeatable metrology measurements of gate oxide thickness is to clean the wafer immediately before every measurement. A fully effective cleaning procedure, whether chemical or thermal, must be carefully controlled and can take 5-15 min or more.³ Even then, very stable measurements are hard to achieve because the rate of apparent film growth is much faster (up to 0.1 nm/hr)⁷ immediately after cleaning. This can make the required repeatability of 0.006 nm difficult or impossible to attain because this growth can place doubt in the accuracy of the measurements. In addition, cleaning some wafers to achieve stable metrology leaves the remaining wafers with organic contaminants that may have the potential to cause defects in the ultrathin oxide layer.³

Cluster tool processing

Many manufacturers are now fabricating polysilicon/SiO₂ gate structures using cluster tools that offer separate process chambers that are linked by an isolated vacuum chamber containing a robot that transfers wafers between chambers. These gate-stack cluster tools form both the gate dielectric and the polysilicon gate electrode without exposing the ultrathin gate oxide to MACs in the fab environment. In 1997, the ITRS (then the National Technology Roadmap for Semiconductors) recognized this as an important driving factor for selecting tools when it stated, "Interface layers will have more influence over device performance which will require new levels of contamination and defect control leading to more in situ and single wafer processing and clustering."⁸

In addition to eliminating the MAC problem (on the gate dielectric), it is more efficient to produce gate structures in a cluster tool. Cycle time in a cluster tool can be up to 90% less than traditional processing, and cluster tools require minimal operator support.⁹

In traditional batch processing, after the gate oxide is grown, the wafer may be stored for minutes, hours or even days before the polysilicon gate electrode is deposited in a separate processing tool. In addition to the problem of MAC adsorption during these holding times, both processing steps require handling of the wafers. Errors may result either from improper handling or improper processing. As an example, a batch of wafers may accidentally be put through the polysilicon deposition chamber twice. The double deposition of polysilicon requires the whole batch of wafers to be scrapped. In cluster tools, all the handling is done by robots, reducing the potential for human error.

Metrology for ultrathin gate oxides under polysilicon

Unfortunately, conventional thin-film metrology tools have, to date, not been able to reliably measure the gate structures produced in the newer gate-stack cluster tools. The conventional approach is to monitor the SiO₂ dielectric thickness and uniformity with a separate monitor wafer (processed in the cluster tool but without depositing the polysilicon). However, this reduces wafer throughput, increases the cost to produce a wafer, and does not provide any information about the polysilicon/SiO₂ interface. In addition, the monitor wafers are subject to all the metrology problems of separately processed wafers described above. An alternative to cleaning the monitor wafers before measurement is to subtract out an estimate of the MAC thickness. Subtracting out the MAC thickness may be viable if the MAC adsorption rate is relatively constant within a fab, and if one assumes that MAC growth is predictable and that the variation from wafer to wafer in the first few hours after oxide deposition is small. Given this, the gate dielectric can be measured and the estimate for MAC thickness, based upon the time elapsed since deposition, can be subtracted to give an estimate of the actual oxide thickness. A significant problem with this approach arises when trying to match tools at different fabs. The growth rate will differ among fabs, making it difficult or impossible to achieve adequate matching.

A much better solution is to eliminate separate monitor wafers and measure the thickness of the gate dielectric underneath the transparent polysilicon. Multi-wavelength laser ellipsometry and new algorithms developed at Rudolph Technologies make possible accurate and repeatable measurements of gate oxides as thin as 2.0 through ~150 nm of polysilicon. This method has the added benefit of simultaneously measuring the integrity of the entire gate structure. All measurements presented in this article were made using a Rudolph Technologies S200-ultra ellipsometer having multiple laser wavelengths, variable spot size and the ability to simultaneously acquire data at multiple angles of incidence.

Metrology challenges

One difficulty in reliably measuring ultrathin gate oxide films under polysilicon is due to normal process variations in temperature, pressure, gas flow and gas source that occur during polysilicon deposition. These variations can cause changes in the optical properties of the polysilicon that affect the accuracy of film thickness measurements of the underlying SiO_2. The amorphous volume fraction (Vf) of the polysilicon defines its optical properties, and therefore is a necessary component of any model attempting to measure intact gate structures.

A recent test on a set of wafers showed the significance of polysilicon deposition parameters. The V f of the polysilicon was found to change almost linearly with temperature in the 600-620°C range. The V f of the wafers varied from a low of 12% (processed at 620°C) to a high of 17% (processed at 600°C). Meanwhile, increasing the gas pressure in the 150-500 mTorr range had the opposite effect of temperature, increasing the V f from 12% to 17%.¹⁰

The Vf of polysilicon has been found to vary both from wafer to wafer and across individual wafers. If the gate oxide measurement is affected by changes in polysilicon Vf, reliable measurements of gate oxide thickness may be unattainable. To accurately check the uniformity of the gate oxide deposition, the polysilicon Vf must be accurately determined at each measurement site and taken into account in the gate oxide film thickness measurement.

A second major difficulty is presented by the rough surface of the polysilicon. It is difficult to model the ~2.0-3.0 nm roughness and the layer of native oxide that develops when the polysilicon surface is exposed to the fab environment. It is common to model the polysilicon roughness and polysilicon native oxide as a single parameter since no process-relevant information is lost by doing so.¹¹ To reliably measure gate oxide thickness, one must accurately characterize these parameters in a way that differentiates measurement of this top oxide and its adsorbing MACs from the measurement of the underlying gate oxide. Although the morphology of the native oxide on top of the polysilicon may be significantly different than that of a thermally grown gate oxide that is beneath the polysilicon, they are both thin SiO₂ films. Any model attempting to reliably measure gate oxide under polysilicon must be able to account for the MAC growth on top of the polysilicon without resorting to cleaning or growth subtraction. These approaches would result in the same long-term repeatability issues as those experienced by a single-layer gate oxide.

Therefore, a complete model of the gate structure must account for all of the following: gate oxide thickness, polysilicon thickness, polysilicon Vf, polysilicon surface roughness, native oxide on top of the polysilicon, and the MAC adsorption on top of the entire structure. Models that fix the polysilicon Vf or any of the polysilicon surface effects to obtain repeatable measurements cannot obtain robust results over a prolonged period, or from fab to fab.

Optimal metrology

Reflectometers are commonly used for process control because of their small spot size and rapid measurements. However, reflectometer accuracy degrades rapidly when measuring films thinner than ~50 nm, so they are not very useful in measuring single-layer ultrathin gate oxides. Because of their superior thin-film repeatability, ellipsometers are typically used to measure thin gate dielectric films.

For measuring polysilicon/ultrathin SiO₂ gate structures, high light intensity is critically important to achieve fast measurements at high repeatability. Laser ellipsometers provide 1000× more light intensity than is available in a white light source spectroscopic ellipsometer at any wavelength. This higher laser light intensity provides the high signal-to-noise ratio required for high repeatability, high throughput and ultrathin gate oxide control under polysilicon.

When measuring the multiple parameters needed to define the polysilicon/SiO₂ gate structure, a single laser wavelength is not adequate. Ellipsometric measurements using at least two wavelengths are required to resolve the multiple parameters that must be measured to completely define the polysilicon/gate oxide film stack. Also, because polysilicon becomes opaque at shorter wavelengths, wavelengths of >500 nm are preferred.

Because the surface of the polysilicon is rough, using a very small spot size that would allow on-product film thickness measurements will produce polysilicon thickness results that are accurate, but unloading and reloading the wafer for subsequent measurements leads to repositioning errors of a few microns that degrade polysilicon thickness reproducibility. Therefore, a larger spot size that provides a more representative measurement due to its area averaging effect is an advantage when measuring on blanket wafers during process development and tool qualification. A spot size of ~2 mm was used.

The multi-parameter model

The four-parameter polysilicon/gate structure used in this model is shown on the left side of Figure 1a. The model is designed to measure the thickness of three layers (the thickness of an upper layer of native oxide on the polysilicon, the polysilicon thickness, and the thickness of the gate oxide). The fourth measured parameter is the polysilicon Vf. We will discuss the strategy for measuring each of these parameters separately.

The polysilicon surface roughness and its native oxide are modeled as a single layer, but a layer of MACs that forms on the native oxide can affect the accuracy and reproducibility of the gate oxide thickness measurements.

Because the polysilicon roughness and its native oxide remain stable at each measurement site, we combine them and the adsorbed MAC layer into a single measured parameter, which we refer to as TopOx. This allows the MAC growth on the polysilicon native oxide to be measured.¹¹

The T_Polysilicon was measured using the ellipsometer and the Vf_Polysilicon was determined from the measured n and k using effective medium approximation (EMA). This model represents the optical constants of a heterogeneous material through a linear combination of two (or more) of the optical properties of the constituent material. The general formula for an EMA is:

Where: e_S= dielectric function of the heterogeneous material

e _i = dielectric function of the i ^th constituent

Vf i = volume fraction of the i ^th constituent

Materials typically modeled using an EMA are polysilicon, hemispherical grained silicon, oxynitride, and SiO₂ + Si₃N₄.

The fourth measured parameter in the polysilicon/SiO₂ structure, the underlying gate oxide thickness, was fit using a standard Cauchy model. This type of model describes the optical constants (n and k) as a function of wavelength, and is generally used for smooth monotonic amorphous materials such as SiO₂, Si₃N₄, resist and polyimide.

4. Ultrathin gate oxide measurements taken through 150 nm of polysilicon. The long-term repeatability was ¡À 0.0032 nm (1 s).

Because the TopOx native oxide film thickness is stable, the measured slope of MAC adsorption for a TopOx film and a single-layer gate oxide film would be expected to be similar when both are exposed to the same environment.

The film thickness measured over a seven-day period for a TopOx film and a single-layer gate oxide film are compared in Figure 1. Both films showed an apparent thickness growth of ~0.05 nm. Despite the MAC growth on TopOx, the measured gate oxide thickness remained stable at 2.34 nm ±0.0014 nm (1 s), indicating that the polysilicon/gate-stack model properly decouples MAC growth on TopOx from the gate oxide film thickness measurement.

It can be seen that the polysilicon thickness remained stable at 159.46 nm ±0.1758 nm (1 s) over the seven-day period, indicating decoupling of the MAC thickness growth from the polysilicon film thickness measurement. With one measurement, the gate-stack metrology model simultaneously calculated the thickness of TopOx, polysilicon, and the underlying gate oxide plus the V f of the polysilicon (Fig. 2).

Uniformity

Gate oxide thickness uniformity across a wafer is an important process control parameter. If the gate oxide is too thin in some places, the ICs in that portion of the wafer may fail. This would lead to lower yield and erode profits. On the other hand, if the gate oxide is too thick, those ICs will not have the desired speed and low-power performance. Yield will be maximized when the gate oxide thickness is close to the specified value across the entire wafer.

The new polysilicon/gate metrology method can accurately measure gate oxide thickness uniformity across a wafer because it determines all four modeled parameters with a single measurement. Across the wafer, non-uniformities in the polysilicon Vf, or other optical properties, have been shown to not affect the underlying gate oxide measurements.

Figure 3 shows a 13-point gate oxide thickness map. The thermally grown gate oxide was ~2.9 nm thick. The gate oxide thickness measurements were made through ~150 nm of polysilicon. The gate oxide thickness across the wafer was found to have a 1 s variation of 0.0133 nm.

Long-term measurements

In an evaluation of the long-term repeatability of this method, six wafers were monitored over a seven-day period. Four of the wafers had SiO₂ films of ~2-3 nm, covered with ~150 nm of polysilicon (slots 2, 3, 7 and 8). A layer of native oxide formed on the top of the polysilicon. Two additional wafers had a single-layer gate oxide in the same thickness range but no polysilicon cap (slots 1 and 6).

Gate oxide thickness measurements of the capped wafers are shown in Figure 4. The long-term repeatability of these results were 0.0014-0.0032 nm (1 s). This level of measurement repeatability exceeds the stringent process control requirements set by the ITRS for gate oxide thickness. Therefore, this technique can be used by process engineers to monitor gate oxide deposition processes through the year 2005 and beyond.

Figure 5 shows the results from the polysilicon measurements of the capped wafers. The thickness of the polysilicon on the wafers was 155-165 nm. The long-term repeatability of the polysilicon thickness measurement was 0.174-0.223 nm (1 s). The polysilicon Vf was 8-11% with a long-term repeatability of 0.27-0.36% (1 s), which shows a high sensitivity for detecting small changes in Vf. This gives process engineers the required repeatability and sensitivity necessary for tight polysilicon deposition process control, and allows the model to compensate for changes in polysilicon composition across a wafer.

The apparent growth in the measured thicknesses of the TopOx layer of the polysilicon capped wafers and the uncapped gate oxide wafers is shown in Figure 6. All oxide layers appeared to grow over the seven-day period. The total growth varied from 0.04 to 0.065 nm.

On the uncapped wafers, the MAC-induced variations in measured thickness would lead to unacceptable repeatability. The process engineer would not be able to distinguish drifts in the process from apparent differences in thickness due to contaminants.

However, using the new polysilicon/gate model to measure the capped wafers, the gate oxide thickness measurements were immune to the MAC-induced apparent growth of the TopOx layer. Once again, it is important to note that a single measurement provides the data for all four model parameters charted in Figures 4, 5 and 6.

7. A long-term study was undertaken using three additional wafers. The wafers were prepared with ~120 nm of polysilicon with a volume fraction between 9 and 10%. The thickness of the top oxide was ~3.0 nm and grew up to 0.3 nm over the course of the 23-day period. The long-term repeatability of the gate oxide measurements is shown and was ± 0.0041 nm (1 s).

A longer-term study was undertaken with three wafers in another fab. The gate oxide was determined to be ~2 nm and the polysilicon gate electrode layer was found to be ~120 nm thick with a Vf, depending on the location on the wafer, varying from 9 to 10%. Over a 23-day period, the TopOx layer grew ~0.3 nm. This growth rate is significantly higher than those in the previously described trial, as the wafers were newly processed. The long-term repeatability of these wafers is shown in Figure 7. Even over this prolonged period, and with up to 10% apparent thickness growth of the TopOx layer, the long-term repeatability was ¡À0.0041 nm (1 s). This demonstrates that the new polysilicon/gate film-stack model returns repeatable gate oxide measurements despite significant changes in the TopOx layer.

Applications

The method has been shown to measure gate oxide thickness and polysilicon thickness and Vf accurately and with the long-term repeatability required for process control. As the use of cluster tools proliferates in the diffusion area for gate-stack processing, the need to make accurate and repeatable gate oxide measurements will require a methodology that can account for multi-layer/multi-parameter structures subject to MAC growth.

This method is equally as valuable in the traditional processing method, where the gate oxide is grown in a diffusion furnace and the polysilicon is then deposited in another tool and after a storage period. Monitoring the gate oxide thickness after polysilicon deposition can be used to monitor the quality of the polysilicon/SiO₂ interface. Because the polysilicon thickness and polysilicon Vf measurements are robust, the model provides a check for processing errors. If a problem such as double deposition is discovered, the wafers can be scrapped immediately before further time and resources are wasted.

Future work

To maximize the output of cluster tools, it is important to measure on product wafers. As wafer size increases, the expense of the test wafers, and the production capacity lost to processing them has made test wafer metrology increasingly inefficient. In addition, the risk to all product wafers between test wafer runs is high. A method for measuring the four parameters in a gate structure on patterned wafers is being developed that will allow measurements in scribe-line test sites.

Conclusion

Process control of gate structures is critical and is becoming more challenging as devices shrink. The novel method presented in this paper has been demonstrated to measure ultrathin gate oxides under a thick layer of polysilicon with better than 0.005 nm repeatability. This method also measures polysilicon thickness, its amorphous/crystalline volume fraction, and the combination of polysilicon roughness, native oxide and MAC adsorption on the wafer surface.

This capability to measure and characterize the entire gate structure is extremely valuable in cluster tool processing, where the whole structure is created in a single tool. It is also valuable where the gate oxide and polysilicon are deposited in different tools, as errors in processing and/or handling between the gate oxide formation and the polysilicon deposition can be determined at an early stage.

David M. Leet is the director of transparent metrology and technical strategic planning at Rudolph Technologies Inc., where he is responsible for developing new transparent metrology products, transparent and opaque applications and strategic roadmap planning. He received his Ph.D. in materials science from the University of Illinois at Urbana-Champaign.

Daewon Kwon is an advanced system scientist at Rudolph Technologies, responsible for developing new metrology products, product extensions and improvements. He received his Ph.D. in physics from the University of Oregon.

George Collins is the director of marketing at Rudolph Technologies. He received his Ph.D. and M.B.A. from Rutgers University.

Jana Clerico is the director of marketing communications at Rudolph Technologies. She received her B.S. in electrical engineering from Stevens Institute of Technology and an M.B.A. from Fairleigh Dickinson University.

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