Wafer Cleaning Confronts Increasing Demands
Aaron Hand, Managing Editor -- Semiconductor International, 8/1/2001
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As feature sizes shrink, contamination becomes more problematic, encouraging manufacturers to keep the wafers cleaner throughout the manufacturing process. This means that, at the front end of the line, they are cleaning wafers after each step. The number of cleaning steps is on the rise at the back end as well, simply because of the increased number of metal layers, each of which needs to be cleaned (Figure 1).
The introduction of new materials such as copper and low-k dielectrics, shrinking linewidths and higher aspect ratios, and increased wafer sizes are all contributing to new demands in the cleaning arena, including additional cleaning steps, more advanced cleaning technologies, and more integrated cleaning solutions.
Between the etch/implant and deposition/anneal steps, a wafer passes 24 times through photoresist removal, residue removal and rinse/dry steps for a logic chip with six metal layers, according to Novellus Systems Inc. (San Jose). "Classically, chipmakers just stripped off the resist after etch," said Wilbert van den Hoek, executive vice president of integration and advanced development at Novellus. "Today, they have to deal with all kinds of residues. That's a little more difficult than just removing organic resists."
Since acquiring Gasonics (San Jose) in January, Novellus has been focusing on integrating the three-step cleaning process into one process. Part of the reason for this is to protect new materials such as low-k dielectrics and copper, which are very sensitive to the atmosphere. Keeping the materials inside the same tool while completing various processes would help protect them.
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"We no longer talk about resist strip," van den Hoek said. "We talk about cleaning overall. We do everything in the same process chamber."
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Don Mitchell, president and CEO of FSI International Inc. (Chaska, Minn.), also speaks of integrated cleaning clusters. "It's becoming more important with the smaller linewidths because it becomes more detrimental to those circuits if they are exposed to air or other contaminants," he said.
Mitchell talks about the challenges that cleaning faces — copper and low-k materials among them — as opportunities for the cleaning industry. "In some cases, it simply means changing the mixture of the chemicals. But in other cases, it requires a whole new solution."
Low-k, copper hazards
Low-k dielectrics present significant challenges to wafer cleaning because chemicals must be developed that will not attack the materials. This becomes even worse with ultralow-k materials, whose porosity makes them more susceptible to damage. Although not in volume manufacturing scenarios yet, chips with low-k dielectrics and copper interconnects will require a whole new set of chemical solutions, said Ernst Gaulhofer, vice president of field support and process applications for SEZ AG (Villach, Austria).
It is difficult stripping photoresist, for example, without breaking through the low-k dielectric, van den Hoek explained. Cleaners must get through a chemically inert resist crust. "You really need some force to get through the crust," van den Hoek said. "It's not so easy if you have a low-k dielectric material (below the resist). You have to do it without damaging the low-k material. ... It's become pretty high-tech to remove photoresist these days." Incomplete removal of resist and residue can significantly increase the k factor.
With copper, the danger is etching things that are not meant to be etched, said Scott Prengle, manager of new technology development, product marketing group, at DNS Electronics (Carrollton, Texas). Although copper offers improved interconnect speeds, it is more susceptible to corrosion.
Single-wafer processing
One method for controlling the cleaning process as wafers become more complex is to move to single-wafer cleaning methods. At the front end of the 0.18 µm node, the standard in wafer cleaning is certainly batch processing, using wet benches or spray tools. But a number of factors are encouraging a shift to single-wafer cleaning systems.
Cleaning one wafer at a time offers the control that is becoming increasingly important to achieve necessary yields, with good repeatability and conformity. And as environmental issues come to the fore, single-wafer cleaning provides a means to conserve the chemistries being used, reducing waste and simplifying recycling efforts.
Not to say that everybody has immediately jumped on the single-wafer bandwagon. In its usual conservative manner, the semiconductor industry has been slow in adopting single-wafer systems, which have been around for more than 10 years. They do not offer the throughput that batch systems can offer, but the industry is finally becoming more motivated to accept those throughputs in return for the benefits single-wafer cleaning offers.
DRAM manufacturers, for which throughput is a more critical issue, are still not likely to be moving to single-wafer methods anytime in the near future. But foundries, primarily in Southeast Asia, have already begun single-wafer cleaning, according to SEZ's Gaulhofer.
SEZ has foundry customers in Taiwan for its single-wafer systems, and others in Taiwan and Singapore have recently initiated production. "People recognize that single wafer has a good future," Gaulhofer said. Just as chemical vapor deposition (CVD) systems and plasma etchers have moved from batch to single-wafer systems, so too will cleaning systems, he said, especially for 0.13 and 0.10 µm nodes. "Logics and foundries are very much interested, and even microprocessor companies," he said.
Cleaning just one wafer at a time instead of a whole batch makes it easier to optimize the process, improving uniformity across the wafer. Although wafers at the 0.18 µm node are still using wet benches, chipmakers are already seeing a yield drop at 0.15 µm, according to Gaulhofer. "You get quite a good yield with single-wafer cleaning," he said, noting that non-uniformity is generally less than 1% with single-wafer processes, and very often down to 0.7%, depending on the chemicals used.
Although not yet to the 250-300 wph throughputs typically attained with batch wafer cleaners, single-wafer systems have reached throughputs of 100-150 wph by incorporating two to four wafer chambers, Gaulhofer said.
Dainippon Screen (DNS, Tokyo) has had single-wafer cleaning tools for several years, but they have always been limited to niche applications, mainly because of the throughput issues, according to Prengle. "DNS has been a batch cleaning supplier for a long, long time," he said. The dynamics of the 300 mm fab will require more single-wafer cleaning, he said, with improved control and uniformity.
Metal corrosion
Until only recently, single-wafer cleaning has been limited to the back end of the line, where HF- and fluorine-based chemistries are more likely to attack the metal during post-metal cleans. In batch processes, it takes longer for the water and chemicals to leave the wafer surface, prolonging the possibility of metal corrosion, Gaulhofer explained.
SEZ and other cleaning system manufacturers are working closely with chemical vendors to develop chemicals specifically for single-wafer systems. The chemicals must be more aggressive, formulated for short cycle times. "It switches on, switches off," Gaulhofer said. "Everything is gone immediately, and it's really gone."
Some manufacturers have already been using single-wafer methods to do aluminum oxide cleans for 0.25 and 0.18 µm nodes, Gaulhofer said, adding that next in line is 0.13 µm and copper dual-damascene processing.
The introduction of copper is where single-wafer cleaning becomes that much more important, because copper is even more susceptible to corrosion. The standard for following chemical mechanical polishing (CMP) processes is to use scrubbers to clean. But, as linewidths shrink, chipmakers are suffering from silicon processes that remain on the wafer, Gaulhofer said. So manufacturers are moving to chemical cleaning for post-CMP. But these solutions are likely to etch and corrode copper interconnects.
Another important cleaning step is back-side cleaning. But copper and other new metals can cross-contaminate the wafer in batch cleaning.
Environmental plus
Single-wafer cleaning systems are also better for the environment, for one because they require much less use of water — 10-20× less, in fact, according to Gaulhofer. With single-wafer systems, the water covers the surface for 10-15 sec, then is shut off, as opposed to batch systems, which require enough water in the bath to surround the entire batch.
"The only liquid that matters is the liquid that's touching the surface of the wafers," Prengle said. Not only do the cost-of-ownership dynamics look better for single-wafer cleaning, he said, the environment is better off with the reduced effluents and waste.
"In Hsinchu (Taiwan), there are so many new fabs and they need so much water," Gaulhofer said, noting that those fabs are having trouble getting the water they need for production. The situation will only get worse with the introduction of 300 mm wafers, he said, because they will require even more water.
Dry cleaning
Of course, one way to reduce the amount of water used is to move to a dry cleaning solution. "Dealing with chemical waste is becoming a huge issue," van den Hoek said, adding that chipmakers are typically the largest users of city water that's available. "It's a problem if they contaminate that water."
A wet step is still necessary in dry cleaning, van den Hoek conceded, but Novellus is now trying to achieve cleaning with just a DI rinse. "We're very far along in the dry process to be able to use just DI water," he said.
Copper and low-k materials may also bring about an increased use of dry cleaning solutions, which are mostly in development stages at this point. Despite various pronouncements of its death, wet cleaning is still going strong, but several companies are developing a variety of dry cleaning methods.
FSI, for example, has developed a completely dry cryokinetic technology that does not damage copper materials or low-k films. The process uses high-speed cryogenic aerosols of inert gases to remove particles from wafer surfaces.
Applied Materials (Santa Clara, Calif.) recently acquired Oramir Semiconductor Equipment Ltd. (Yoqneam, Israel), which makes a wafer cleaning technology that uses a laser to ablate post-ash residues.
Novellus is making a move to dry cleaning technologies for a number of reasons. As the industry moves to more complex features, dry cleaning can offer more efficient removal of complex residues, the company says, without attacking or contaminating underlying device materials. Dry cleaning also offers better penetration and extraction than solvents from high aspect ratio vias.
"Solvent has difficulty getting into those features," van den Hoek said. "Moving those steps into a dry processing regime clearly is the way to go."
In terms of cost of ownership, dry cleaning can offer advantages in that it eliminates solvent and disposal costs, and reduces footprint requirements, according to Novellus.
SEZ announced in June that it was joining efforts with Axcelis Technologies Inc. (Beverly, Mass.) to study the benefits of integrating dry and wet cleaning technologies for FEOL and BEOL photoresist removal and post-etch cleaning, particularly for copper, low-k and dual-damascene applications. The goal is to decrease chemical usage and improve cleaning process cycle times, said Michael West, vice president of strategic business development for SEZ, in a statement. The team will combine Axcelis' dry plasma cleaning with SEZ's single-wafer wet technology, he said. By combining the two approaches, the companies expect to reduce process times and improve process results.
Conclusion
No matter how the industry decides to tackle the increasingly complex wafer cleaning issues that lie ahead — dry vs. wet, single-wafer vs. batch — it is clear that the cleaning process itself will continue to take on more importance.
Low-k dielectrics and copper interconnects are the materials on the radar screen today, but any new material that comes along will likely require an innovative cleaning solution.
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