Embedded Distributed Capacitance — an Enabling Technology

The power supply current requirements of some high-end processor chips is now at 50 A, and will increase to >100 A in a few years, according to Larry Smith and Ray Anderson of Sun Microsystems. A substantial fraction of this current will be switching at the clock frequency and sub-harmonics, depending on the precise microcode running. If design and technology advances in the power distribution system (PDS) do not keep up, switching noise and ground bounce will soon limit high-performance systems.

Traditionally, the PDS has been optimized in a four-tiered approach: on chip decoupling capacitance, low-inductance chip attach and package design, discrete decoupling capacitors, and power and ground planes in the package and in the motherboard.

A significant technology advance was introduced by a collaborative program led by the National Center for Manufacturing Sciences (NCMS, Ann Arbor, Mich.). This program focused on the early evaluation of embedded distributed capacitance (EDC), which basically is the use of very thin, high dielectric constant layers between the copper power and ground layers in an otherwise conventional laminate. Boards with this special layer could be used in small organic packages or large system boards.

Measured noise with various EDC layers, compared with conventional FR4. Scale is 5 nsec/div and 500 mV/div. (Source: NCMS)

The performance advantage of EDC layers arises from two features: the thin dielectric and the higher dielectric constant. In the case of the 3M C-PLY material, the dielectric thickness is 8 µm and, filled with barium titanate powder, the composite dielectric constant is ~20. This should be compared with conventional FR4 power and ground layers, with a minimum thickness of ~100 µm and dielectric constant of 4.

Todd Hubing, an electrical engineering professor at the University of Missouri (Rolla) and technical lead on the performance analysis, suggests that discrete decoupling capacitors can only play a role below ~100 MHz, and then only if the mounting inductance is kept low. Above 100 MHz, all the decoupling comes from the interplane capacitance. However, above ~200 MHz, resonances in the planes, from the physical size of the board, can have significant impact on the rail collapse noise..

EDC layers help solve both problems. The thin layer and high dielectric constant provide a distributed capacitance more than 60× a conventional board. And this is all low-inductance capacitance. The low impedance means series resistance from the copper layers can damp out the resonances. For high-frequency noise, the thin power and ground layers look like a very lossy transmission line.

In the NCMS study, only a few materials were considered and only preliminary reliability and manufacturability studies were performed. Even so, the recommendation of the five fabricators was that "... they were able to build test vehicles using standard processes or slightly modified processes. Each fabricator feels they are ready to accept small volumes of prototypes using these materials."

There is still much work to do before this new material system is ramped to high volume. Cost models need to be built, yield needs to be determined, the long-term material reliability needs to be evaluated and design rules need to be established. A follow-on study has begun as part of a NIST ATP award. The Advanced Embedded Passives Technology Consortium (AEPT) has been formed with more than 15 member companies and organizations.

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