IC Package Solutions for High-Performance Memory

Chip-scale or chip-size packaging (CSP) is in wide use throughout the industry, providing the solutions for applications that enable a reduced product size-to-function ratio. Portable or hand-held electronics is a natural target. Digital cameras and camcorders, for example, must consider ease of use, lighter weight and performance. Telephones, pagers, personal communicators, palmtop computers, industrial and automotive electronics, personal GPS, and medical and diagnostic products are all viable candidates for more efficient device miniaturization. Memory devices are the first commodity-type products in the market to adapt CSP in high volume. However, DSPs, controllers, CPUs and any number of application-specific IC devices are also prime candidates for chip-scale packaging.

In regard to memory packaging applications, performance has become a key issue. The RDRAM and DDR (double data rate) SDRAM families, for example, require the shortest possible signal path to achieve the performance criteria demanded for complex data and graphics processing. The lead-bonded µBGA¹ package, as well as the wire-bonded µBGA package technologies, provide the short interface necessary to meet the performance requirement and furnish a mechanically robust finished product. The package technology represents the patented system of materials and die-to-package interface design that is physically compliant. These attributes combine forces to compensate for the wide differences in the coefficient of thermal expansion between the silicon die and the circuit board structure. This package technology has the capability to adapt to a variety of die designs and is manufactured using methods consistent with existing packaging methodology. The compliant package concept has gained wide acceptance in the industry and is supported by a strong and growing material and equipment supplier infrastructure. Outwardly, a lead-bonded µBGA package and wire-bonded µBGA package look alike. The cross-section illustrated in Figure 1 details the µBGA package construction.

1. The lead-bonded µBGA package material system and integrated bond lead design provide a compliant (stress-absorbing) structure that will meet the most demanding electrical and mechanical performance.

Higher-I/O packages can be furnished using two conductor layers (referred to as "two-metal tape"), relying on plated microvia holes for side-to-side interface. This two-metal-layer process allows for very narrow circuit routing (<0.05 mm) and the benefit of an "on-package interconnect" for power, ground and clock lines.

(Note: When the contact array pattern exceeds the area defined by the silicon die, one may consider an alternative interface pattern, a pattern that will distribute ball contact to the area both outside and inside the die perimeter.)

Because the device units are processed using conventional die-attach and wire-bond machines, handling and automated transfer of the product through the process steps is very efficient. And although each device area is often relatively small, multiple-unit arrays can be closely clustered on the flex-tape material. A common width for the polyimide flex-tape is 48 mm. As an alternative to the 48 mm-wide flex-tape format noted, suppliers can also furnish flex-tape in 35 or 70 mm width. Before the device assembly can begin, however, the basic flex-tape material must go through a die-site preparation process. In this process, the flexible polyimide surface is furnished with a proprietary elastomer spacer pattern (nubbins) at each die attachment site. The converted flex-tape is then mounted to the carrier frame and transferred to the package assembly operation ready for die attach. Figure 2 details the general assembly flow for the µBGA package, processing several devices on the rigid frame carrier.

2. The process flow for a µBGA package is simple yet unique in the use of the formed copper core lead and low modulus encapsulation process.

3. The controlled “S” shape created during the lead bonding process, and the limited flexibility of the die attach and encapsulation material, contribute to provide an overall compliant, stress-absorbing package structure.

The lead bond systems employed were originally developed for wire bond applications (although no wire is required for the lead-bonded µBGA package assembly). The bond tool and software have been specially modified for the lead bonding process. The bond tool individually captures each lead suspended within the window on the flex-tape.

The encapsulation process may adapt vertical dispensing or a forced injection of the elastomer encapsulation. In preparation for encapsulation, a temporary coverlay film is applied to one or both sides of the carrier frame. For the injection method, the film provides a closed membrane that will contain the encapsulation material. The flex-film carrier frame is transferred into a universal mold fixture, and an injection needle is inserted into an opening provided in one end of the coverlay membrane material. The liquid elastomer, although injected with pressure, is drawn through the array of die with a vacuum applied at the opposite end of the flex-tape frame carrier. The injection process is completed in 50 sec and, with the simultaneous encapsulation of two flex-frame carriers at a time, the throughput can reach 120 carrier frames/hour. After the injection process and curing of the encapsulant, the coverlay film is removed.

Flux is applied to each ball attachment site using a pattern printing process. Screen print deposition provides a consistent 20 µm-thick pattern of flux on each ball attachment site. In addition, using a flux with high adhesive properties adequately holds the solder sphere in position throughout the reflow solder process. The minimum land pattern diameter provided on the µBGA device using 300 to 350 µm diameter sphere contacts is 0.20 mm, but 0.25 and 0.30 mm diameter lands are most common. A uniform technique for mass ball placement is a must for volume CSP device packaging. There are several excellent systems available for ball placement. Some systems are designed to apply flux with the screen process described. Others may employ a pin-transfer technique, and others still have developed attachment and reflow processes that do not require flux.

Several alloy compositions can be considered and, although each has a rated liquid level, one or the other may be selected to meet specific criteria. When selecting a supplier for the spheres, one must also consider solder ball tolerances, sphere uniformity and its impact on contact array coplanarity. In addition, there are several ball alloy options and attachment techniques to choose from. The µBGA and wire-bonded µBGA package is furnished standard with an Sn63/Pb37 alloy, a collapsible solder sphere. The eutectic solder has a melting point of 183°C. Lead-free alloy compositions are also available — the specific composition is typically specified by the customer. The nominal diameter of the solder sphere in production for the center lead bond RDRAM is 350 ±50 µm.

The three primary reflow heating methods being used for high-volume BGA production are infrared (IR) radiation, forced hot-air convection and thermal conduction. The IR process produces the least satisfactory results, and a unique profile is required for each package design. Other problems may be experienced due to temperature variation across the carrier strip and variation in oven loading. Consequently, IR reflow is not recommended. Both the forced-air convection and the conduction systems provide more satisfactory results. Temperature is more uniform across the strip, and a single profile can be maintained for different product configurations.

Devices are typically marked on the back surface of the silicon die before singulation. The use of laser or epoxy ink for marking is optional; however, the laser marking process may prove most efficient because the system can be programmed for each device type and will allow serialization. The ink marking method, on the other hand, requires custom print plates for each device type. Following the marking process, devices are inspected and can be electrically tested in a strip form prior to singulation.

Singulation of the packaged device from the flex-film carrier must be very precise. Several techniques have proved successful. For example, sawing, rotary and straight blade cutting, as well as die-punch methods, have proven to be efficient. Each method has advantages and disadvantages — the saw, rotary and straight blade cutter, for example, can be programmed. Programmable systems allow for several package variations requiring minimal tooling. The die-punch methodology requires precision tooling that must be prepared for each device type and its unique die outline profile. However, die punching will provide the highest throughput.

Several manufacturers have developed variations of the chip-scale package, utilizing a broad variety of packaging materials. The selection of one packaging concept over another may be influenced by the ability of the device to qualify for the specific product use environment criteria. Most of the alternative package structures, for example, require an epoxy underfill because operating temperature excursions cannot be absorbed equally between dissimilar materials. Most of the physical stress is transferred to the solder connection between the contact sphere and package as well as the attachment site on the circuit board.

4. The chip-size device shown is typical of the newer generation of memory die, having center-positioned bond pads and requiring a very short interface to the solder ball contacts.

A strong infrastructure and an efficient, high-yield manufacturing process may prove to be a major factor in controlling package assembly cost. When comparing device packages, consider end-product reliability as well. In addition, the devices must be electrically pre-tested (really tested) and packaged in a format that can provide the performance needed for high-end products as well as the economy demanded for high-volume automated assembly. A chip-scale or chip-size package must also meet the physical criteria established by industry standards and be fully compatible with mainstream SMT assembly processes. Additionally, unlike many of the package choices available, most companies will prefer a package that, when soldered to the circuit board, has the additional burden of epoxy underfill (as does flip-chip and most rigid package structures) to meet reliability goals. The lead-bonded µBGA package meets JEDEC Level 1 criteria for low moisture retention and, because of its compliant structure, does not require epoxy underfill, even in the most severe environments.

Author Information

Vern Solberg has more than 25 years of experience in the design and manufacture of electronic products. He is a senior applications engineer and technical advisor to in-house and OEM customer engineers and design specialists at Tessera. His current responsibilities are related to CSP application engineering and assembly process development, and he represents the company in several industry standards activities, including IPC, IEC and JEDEC. He previously served as Tessera's director of advanced manufacturing technology for five years. E-mail: vesolberg@aol.com.