The Fundamentals of Overlay Metrology

Overlay metrology equipment historically has had little difficulty meeting state-of-the-art process error budgets through the 0.25 µm technology node. In fact, typical overlay measurement equipment performance has been better than metrology error budget allocations by 20-30%.¹ This can be ascribed to several factors. First is the lavish error budget, compared with critical dimension (CD) metrology (3% of minimum design rule vs. <1% for CD metrology). The second is the relative stability of the overlay measurement target design, which typically doesn't scale (in the wafer plane) with each process generation, thereby presenting similar measurement issues for each successive process generation.

Finally, this historic ease of meeting process error tolerance can also be attributed to the lack of a clear connection to device yield. For CD measurements, clear relations to circuit performance and cost are used to derive specific process control limits.² In the case of overlay metrology, the correlation to final device yield is a much more complex combination of factors and, as such, is much more difficult to determine.

Semiconductor pattern overlay is the measure of vector displacement from one process level (substrate) to another level (resist), usually separated by an intermediate (thin-film) layer. The overlay requirements for a particular device design are typically determined through a combination of CD and overlay excursions.

1. The maximum allowable overlay shift shown as the center-to-center distance.

Overlay error is commonly measured using a variant of the box-in-box test structure (Fig. 2) and is defined as the planar distance from the center of the substrate target (outer green box) to the center of the resist defined target (inner blue box). Overlay measurement involves the determination of the centerline of each structure along both the X and Y axes. Centerline determination utilizes the symmetry around the structure's center such that the error associated with edge determination will tend to cancel from each side of the structure. Conversely, in a linewidth determination, the error associated with each edge combines in an additive fashion.

Overlay measurement uncertainty is a complex function of tool, target and process interactions, and is difficult to quantify. The device overlay tolerance specification is derived from the technology design rules. The circuit performance requirements are compared with established manufacturing tolerances. All error sources — from the mask to the measurement uncertainty — are combined either linearly (most conservative) or are added in quadrature (for Gaussian error distributions) to calculate the overlay tolerance. Successful process control of 0.35 µm process technology was possible through initial stepper/scanner matching and subsequent control of layer-to-layer overlay through the use of X and Y offsets. Process tolerances for the 0.35 µm generation, typically 100 nm on critical levels, were generous enough that the non-normal (multi-modal) behavior and dependence on location within a field did not affect the ability to meet target performance specifications. A typical example of the non-normal nature of the raw overlay measurement results is shown in Figure 3. It is readily apparent from the figure that the actual data distribution is multi-modal and platykurtic.⁴ This form of the data distribution is due to systematic lithography errors.

2. A box-in-box test structure is commonly used to measure overlay error.

The sources of overlay error attributable to the wafer stepper/scanner generally arise from the lens (intrafield) and the stage (grid). Intrafield errors can be further broken out into errors that either are intrinsic to the optics of the stepper/scanner (distortions) or are derived from interactions of the reticle with the stepper/scanner's optical subsystem.

3. A typical example of the non-normal nature of the raw overlay measurement results.

Equation 1 is a mathematical model for all X direction intrafield error terms associated with stepper (a similar equation applies for the Y direction).⁵

δx =α+(δM/M)x₀-θy₀-t₁ x₀ ²-t₂x₀y₀- (1)

Ex₀(x₀ ²+y₀ ²)+Fx₀(x₀ ²+y₀ ²)²+ Residuals

From Equation 1, the terms up to first order in x — offset (α), magnification (δM/M) and rotation (θ) — can typically be controlled from the stepper/scanner. The higher-order terms, trapezoid (t₁ and t₂), third (E) and fifth (F) order distortions are not easily controlled (trapezoid) or are intrinsic to the stepper lens (third and fifth order).

Stage-derived errors may also be divided into those over which the process engineer has control and those that are intrinsic to the mechanical subsystem. As shown in Equation 2, the systematic grid errors are very similar in mathematical form to the intrafield or lens errors shown in Equation 1.⁶ But, unlike the intrafield case, the terms apply across the entire wafer.

δx = α+(δM_g/M_g)x₀-θ_gy₀ +y₀ ²Dx +

Residuals (2)

δM_g/M_g is the wafer scaling coefficient, U_g is the wafer rotation coefficient and D is the stage bow coefficient.

Typically, the stepper will allow direct control over only the scale and rotation terms. Accurate separation of the various error components shown in Equations 1 and 2 is heavily dependent upon both sample plan and model statistics. When establishing the metrology sample plan, it is important to maximize symmetry and spatial coverage. These concepts derive from an understanding of the systematic error components due to the lithography tool. To achieve symmetry, die and intrafield site positions should be chosen so that they are balanced by an opposite die or site (not necessarily within the same field location). For good spatial coverage, measurement locations must be positioned such that they adequately cover the area of interest (wafer or die) in both the X and Y directions. Poor symmetry can lead to incorrect systematic error assessment.

In the extreme intrafield case — one site per field — magnification error will appear as a translation error. Correction of this through an offset term will result in a 2× error at opposing die locations. Poor spatial coverage will also lead to incorrect systematic error assessment. For example, sampling the field in the four corners only will result in exaggerated field magnification terms. This is due to the inclusion of (non-correctable) higher-order (third and fifth) distortion terms. In this instance, adding one or two sites along the die edge (at X=max, Y=0 or X=0, Y=max) will allow for differentiation of the higher-order systematic errors from magnification terms.

Overlay measurement must be sensitive enough to discriminate error components derived from all sources. So it is critical that the contribution of the measurement tool to the total error be minimized and well controlled for all process levels.

Overlay measurement difficulties arise in manufacturing from an interaction of the measurement equipment with the instance of the measurement feature (process variations and target design), primarily due to low edge contrast. Low-contrast edges often result from advanced planarization techniques such as chemical mechanical polishing (CMP), used to accommodate a decreasing photolithography process window. These problems require that implementation of overlay metrology be performed with a deeper understanding of the physics of the measurement instrument and the interaction of the process module with the overlay measurement target. In effect, the sample must be considered to be an optical element of the measurement system.

The inherent, tool-limited measurement accuracy is commonly referred to as tool-induced shift (TIS).⁷ TIS is quantified by measuring the same feature at 0 and 180° (wafer) rotations. TIS is half the sum of the measurements from each orientation. TIS error arises from optical alignment, illumination and aberrations of the system optics. TIS interacts with process conditions, achieving different values for different resist thicknesses, substrate surface roughness, substrate topographies and structure designs.⁸

While it is generally true that minimum TIS results in best overall metrology performance, it is also clear that there is a complex interaction between the various measurement schemes (optics, algorithms, illumination, etc.) and TIS performance on a given substrate. TIS is a very complex function of choice of focus method (e.g. single vs. double grab), optical configuration, and substrate material. It is not possible to accurately predict the TIS response for a given instrument on a new substrate based only on an empirical understanding of the instrument's performance on other materials.

Overlay measurement accuracy errors, if not recognized and accounted for, can produce false systematic stepper/scanner errors. The introduction of systematic measurement errors into a simulated stepper setup data set results in the transposition of those errors to the stepper.⁹ TIS shows up in the translation term of the modeled stepper systematic errors, and pixel scale directly modifies the grid and field magnification (scale) coefficients. If these errors are not properly ascribed to the metrology tool, they will end up as a stepper/scanner input correction, which will further degrade product overlay performance. It is important to accurately quantify and assign the contribution of the measurement tool's error component to the measured value, and to minimize its impact via a hardware modification (e.g. optical alignment/columnation) or software calibration.

The final component of the measurement contribution to the overlay error comes from the measurement precision of the tool. This component is easily quantified by performing repeated measurements of a sample in a carefully designed analysis of variance experiment. All of these sources of measurement error combine to constitute the total measurement uncertainty.

This is an excerpt of an article that appeared in AIP Conf. Proc. 550, Characterization and Metrology for ULSI Technology, Eds: D.G. Sieiler, et al. Copyright American Institute of Physics, 2001. "Critical Issues in Overlay Metrology" appears on p. 346-356.