SEM/TEM of the Month
-- Semiconductor International, 6/1/2001
At the research labs of
Infineon Technologies (Munich, Germany), a team in the nano processes department has demonstrated the feasibility of chip metallization with end-of-roadmap dimensions. The SEM micrograph shows metal lines as narrow as 40 nm with aspect ratios exceeding 4:1 embedded in grooves of an oxide-based intermetal dielectric utilizing damascene technique. Low electrical sensitivity was verified for these metal lines featuring the cross-sectional areas of short, local interconnects for wire lengths exceeding those of the global interconnects expected in such chips. To realize structures with lateral dimensions far below the feature sizes that can be fabricated with today's most advanced manufacturing equipment for lithography, a spacer approach was applied to narrow the mask openings for pattern transfer into the intermetal dielectric. The spacers were removed prior to metallization consisting of PVD of a Ta-based barrier and of a Cu seed layer, followed by Cu electroplating and subsequent CMP processes (TEM insert). This recent achievement gives confidence for a smooth extension of today's interconnect technology until the end of the
International Technology Roadmap for Semiconductors (ITRS). The silicon wafers were processed with today's standard semiconductor manufacturing equipment and processes at
International SEMATECH (Austin, Texas).
Please send submissions for SEM/TEM of the month to Peter Singer, Editor-in-Chief, 58 Summer St., Andover, MA 01810 USA.
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