Interconnect Technology Extendible Into Next Decade
Peter Singer, Editor-in-Chief -- Semiconductor International, 6/1/2001
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In an electrical assessment of these wires, "sufficiently low electrical resistance was verified" for all relevant wire lengths. This effectively demonstrates that neither the fabrication of such ultra-thin lines nor the electrical resistance will be technical obstacles for the ongoing process of chip shrinking.
Lithography tools needed for the fabrication of future chip generations in the 2011-2014 timeframe do not yet exist, but Infineon says it overcame this issue by using a spacer technique to narrow the mask openings for pattern transfer into the dielectric film.
This achievement also demonstrates the extendibility of the damascene technique, where grooves and holes are filled by depositing metal over the wafer, followed by a complete removal of all metal covering the filled structures by chemical mechanical polishing. The silicon wafers used for the demonstration were processed with today's standard semiconductor manufacturing equipment and processes developed for 250 nm feature sizes in the cleanroom of International SEMATECH (Austin, Texas), a consortium of the world's leading semiconductor manufacturers.
Intel Opens 300 mm Research Lab
Intel Corp. (Santa Clara, Calif.) opened what it says is the world's first 300 mm wafer research laboratory. Named RP1 (RP stands for research and pathfinding) and located in Hillsboro, Ore., the $250M facility is the first of its kind dedicated to research in advanced silicon process technologies on the new, larger 300 mm wafers. Intel researchers will use RP1 to develop next-generation photolithography, high-performance transistors, advanced interconnects (copper and optical) and environmentally friendly manufacturing processes (new materials and chemistries).
This new facility will allow Intel researchers to continue to build the world's smallest and fastest transistors. Smaller transistors are faster, and fast transistors are the key building block for fast microprocessors, the brains of computers and countless other smart devices. "Intel's technology teams are organized to move innovations efficiently through the stages of research, pathfinding, development and manufacturing," said Sunlin Chou, senior vice president and general manager of Intel's Technology and Manufacturing Group. "By building RP1 next to D1C, Intel now has all stages of its 300 mm technology pipeline in place to drive the advancement of Moore's Law on a larger wafer size."
RP1 is home to Intel's Components Research Lab, part of Intel Labs. The group develops silicon technologies that are two to three generations ahead of Intel's current manufacturing processes. This new research facility, which has a 56,000 ft2 cleanroom, is adjacent to Intel's D1C (a development fab) and high-volume manufacturing factory, Fab 20. RP1 will help Intel accelerate the process of taking ideas from research into manufacturing.
As a research and pathfinding facility, RP1 is different from Intel's development fabs. Pathfinding is a key crossover phase between research and development. Since RP1 supports 300 mm wafers, it allows Intel engineers to share wafers between research and development. This allows Intel to accelerate the introduction of advanced technologies in future products, which will be manufactured at high-volume facilities. "RP1 represents a unique capability in the industry," said Gerald Marcyk, director of Intel's Components Research Group. "We can conduct research both on a small scale in beakers and a large scale using batches of 300 mm wafers — all in one lab."
Intel Labs, the R&D arm of Intel, is comprised of more than 6000 researchers and scientists in labs around the world. The labs are structured in a "decentralized" manner, with significant internal research capabilities complemented by numerous external research programs with universities, government labs and industry consortia. Intel says this structure is different from traditional, centralized research labs, and allows Intel to tackle a broader range of research projects.
For additional information on wafer processing, go to www.semiconductor.net/wafer
