Exploring the Limits of Gate Dielectric Scaling

		At a Glance
	The more aggressively companies scale transistor dimensions in high-performance devices, the more quickly a high-k material will be needed to replace oxide gate dielectrics. In the first of a two-part series, we consider the extendability and limit of oxide-based gate dielectrics. The absolute limit for oxide/nitride films appears to be 7 Å, but 12 Å may represent the practical limit, since effects of gate leakage or reliability will likely prevent further improvements in device performance.

CMOS transistor scaling,¹ which fuels the multibillion dollar semiconductor industry, is rapidly reaching performance limits with traditional materials. Every 18 months to two years, semiconductor companies find ways to shrink devices by 30%, making circuits switch twice as fast while producing twice the number of die per wafer at half the cost.²

At the core of the digital revolution with today's GHz microprocessors lies a key material that has electrically isolated the transistor gate from the silicon channel for more than 40 years: thermally grown, amorphous SiO₂.

SiO₂ is ideally suited to its role, meeting demands for high performance (speed), low-static (off-state) power and a wide range of power supply and output voltages.³ SiO₂ dielectric currently enables defect charge densities on the order of 10¹⁰/cm², mid-bandgap interface state densities of ~10¹⁰/cm²eV, and hard breakdown fields in excess of 10 mV/cm. Finding a dielectric alternative to SiO₂ with even similar electrical properties clearly presents a significant challenge for the industry.

Key material properties of any new high-k materials include high permittivity or dielectric constant, k, barrier properties to prevent tunneling, stability in direct contact with silicon, good interface quality and good film morphology. The dielectric must also be able to demonstrate its compatibility with the gate material, process compatibility and, of course, high reliability.

Transistor scaling

Circuit performance trends can be characterized through switching time (Fig. 1), which results in rapidly shrinking transistor channel lengths and thinning gate dielectrics. We can analyze improved device performance associated with the scaling of logic device dimensions by considering a simple model for the drive current, ID, of a field-effect transistor (FET).³

1. The continual decrease in gate delays for NMOS and PMOS transistors. (Source: IEDM4)

Initially, ID increases linearly with the applied drain voltage, VD, and eventually saturates to a maximum at VD,sat:

where W is the width of the transistor channel, L is the channel length, µ is channel carrier mobility, and Cinv is the capacitance density associated with the gate dielectric when the underlying channel is in the inverted state.

Assuming constant carrier mobility, to increase ID,sat the value of VD,sat is limited in range because of the high electric field reliability and room-temperature operation constraints. To increase ID,sat would require either a reduction in the channel length or an increase in the gate dielectric capacitance, or both.

For the gate capacitance, consider a parallel plate capacitor,

where k is the dielectric constant (also referred to as ε, and is the relative permittivity here) of the material, ε₀ is the permittivity of free space (8.85 × 10^-3 fF/µm), A is the area of the capacitor, and t is the thickness of the dielectric. This expression for C can be rewritten in terms of teq (i.e. equivalent oxide thickness) and k_ox (dielectric constant of SiO₂) of the capacitor. The term teq represents the theoretical thickness of SiO₂ that would be required to achieve the same capacitance density as the dielectric (ignoring issues such as leakage current and reliability).

For example, if the capacitor dielectric is SiO₂, teq = 3.9ε₀(A/C), and therefore a capacitance density of C/A = 34.5 fF/µm² corresponds to teq = 10 Å. Thus, the actual physical thickness of an alternative dielectric employed to achieve the equivalent capacitance density of teq = 10 Å can be obtained from the expression:

Therefore, a dielectric with a relative permittivity of 16 results in a physical thickness of ~40 Å and teq = 10 Å. Of course, actual performance of a CMOS gate stack does not scale so simply with the dielectric because of possible quantum mechanical and depletion effects from the silicon substrate and gate.⁵

From a circuit performance point of view, one metric considers the dynamic response of the transistors associated with a specific circuit element to the supply voltage provided to the element at a representative (clock) frequency. The switching time is limited by both the fall time required to discharge the load capacitance by the n-FET drive current and the rise time required to charge the load capacitance by the p-FET drive current. That is, the switching response times are given by:³

C_LOAD includes the gate, parasitic junction and local interconnect capacitance. The gate delay, shown in Figure 1, can be related to this switching time through the "fanout," F, of the gate network. A typical value of F is 3 or 4.

The gate stack

2. The interfacial layers between the gate electrode and substrate (~5 Å) can alter the overall capacitance of the gate stack.

Figure 2 provides a schematic of the various regions associated with the gate stack of a CMOS FET (regions are separated to clarify the following discussion). The gate dielectric insulates the gate electrode (polysilicon) from the silicon substrate.

The interfaces with either the gate or the silicon channel region are particularly important in regard to device performance. These regions, ~5 Å thick, serve as a transition between the atoms associated with the materials in the gate electrode, gate dielectric and silicon channel. These interface regions can alter the overall capacitance of the gate stack, particularly if they have a thickness that is substantial relative to the gate dielectric. Alternatively, these interfacial regions can be exploited to obtain desirable properties such as a dopant diffusion barrier or low interface trap densities.

SiO₂, SiO_xN_y and Si-N/SiO₂ limits

Recent efforts in gate dielectric scaling have focused on extending the use of SiO₂ through thinning or introducing nitrogen into the dielectric. Beyond the scaling limit of these known materials, new materials will be required as the gate dielectric to allow further CMOS scaling.

The apparent robust nature of thin SiO₂, coupled with the industry's acquired knowledge of oxide process control, has extended its use for the past several decades in CMOS technology. Even recently it has been demonstrated that transistors with gate oxides as thin as 13-15 Å continue to operate satisfactorily.^6,7

Although high leakage current densities of 1-10 A/cm² (at V_DD) are measured for such devices, transistors intended for high-performance microprocessor applications can sustain these currents. However, it appears that scaling of CMOS structures with SiO₂ gate oxides thinner than ~12-13 Å results in no further gains in transistor drive current, and may well serve as the practical limit for reducing the SiO₂ thickness.⁷ Experiments and modeling have also been done on even thinner SiO₂ films on Si, as a way to determine how the SiO₂ bandgap or band offsets to Si change with decreasing film thickness.^8,9 Modeling studies of the SiO₂/Si interface have predicted that an absolute physical thickness limit of SiO₂ of 7 Å is in agreement with recent experiments.⁸ Below this thickness, the Si-rich interfacial regions from the channel and polycrystalline Si gate interfaces used in MOSFETs overlap, causing an effective "short" through the dielectric, rendering it useless as an insulator.

An equally important issue regarding ultrathin SiO₂ gate oxides has been understanding and predicting oxide reliability. Although there continues to be debate over the detailed process associated with 10-year reliability predictions, more recent projections indicate that oxides down to 14 Å (as measured by ellipsometry) at 1.4 V operating voltage appear to meet requirements.^10,11

In contrast to the high-performance microprocessor market, the rapidly growing market of low-power applications requires transistors with much lower leakage currents (~10^-3 A/cm²).¹² It is clear that a gate dielectric with a permittivity higher than that of SiO₂— and therefore physically thicker — is required to meet low-power CMOS application requirements.

In addition to leakage current increasing with scaled oxide thickness, the issue of boron penetration through the oxide into the channel is a significant concern for threshold voltage shifts.¹³

These concerns have led to materials structures such as oxynitrides and oxide/nitride stacks for near-term gate dielectric alternatives. These structures provide a slightly higher k value than SiO₂ (pure Si₃N₄ has k~7), reduced leakage (since the film is physically slightly thicker), reduced boron penetration and better reliability characteristics.^14,15

Despite encouraging results from a variety of deposition and growth techniques, scaling with oxynitrides/nitrides appears to be limited to t_eq~12-13 Å.¹⁶ Below this, the effects of gate leakage, reliability or electron channel mobility degradation will most likely prevent further improvements in device performance. According to the most recent industry roadmaps, SiO_xN_y and Si_xN_y/SiO₂ dielectrics represent current three-year, near-term solutions for scaling the CMOS transistor.³

Fundamental limitations

Considering current efforts on SiO₂, oxynitrides and even high-k gate dielectrics, several potential fundamental limitations could seriously threaten the continued scaling of all gate dielectrics, regardless of the material involved.¹⁷

First, the electrical thickness of any dielectric is given by the distance between the centroids of charge in the gate and the substrate. This thickness, t_eq, therefore includes the effective thickness of the charge sheet in the gate and the inversion layer in the substrate (channel). These effects can add significantly to the expected t_eq derived from the physical thickness of the dielectric alone.⁵

Dopant depletion in polysilicon gate electrodes also occurs in inversion near the gate dielectric interface. This results in a portion of the polysilicon electrode (~3-4 Å) nearest the gate dielectric interface essentially behaving like intrinsic silicon, adding ~3-4 Å to the effective dielectric thickness. Thus even for ideal, degenerately doped polysilicon gates, it is difficult to realize an overall t_eq<10 Å in MOSFETs using current process technology.

Metal gates offer a possible solution to the gate depletion problem, but the addition of 3-6 Å to the t_eq value from the inversion layer in the silicon channel will remain. Novel device designs will be required to overcome this issue.

Materials considerations

Any new high-k gate dielectric must meet specific criteria to function as a successful gate dielectric.¹⁸ These include permittivity, barrier height, stability in direct contact with silicon, interface quality, film morphology, gate compatibility, process compatibility and reliability.

In the spectral region of CMOS operation (100 MHz-10 GHz), the two main contributions to the dielectric constant (which give rise to the material polarizability) are electronic and ionic dipoles¹⁹ (Fig. 3). In general, atoms with a large ionic radius (i.e. high atomic number Z) exhibit more electron dipole response to an external electric field because there are more electrons to respond to the field (electron screening effects also play a role in this response).

This electronic contribution tends to increase the permittivity for higher atomic number atoms. So it may be concluded that simply introducing insulators with high-Z elements will provide a good high-k gate dielectric solution.

However, this increase in permittivity comes at price: a substantially lower bandgap than that of SiO₂ and therefore a (usually) lower band offset, possibly resulting in higher leakage currents.

We must also consider the thermodynamic and electrical stability in a silicon-based device structure in the selection of suitable dielectric materials. The processing required in CMOS flows may well result in the formation of an interfacial layer, which can result in a lower overall dielectric constant for the gate stack structure. Similarly, polycrystalline dielectric films may be produced, resulting in higher leakage and a variable dielectric constant resulting from grain orientations.

In Part 2 of this series, we will examine the many issues that influence the selection of new high-k dielectric candidates and discuss the most viable and likely candidates.

Conclusions

The industry has enjoyed the fruits of more than 30 years of research and development on the SiO₂/Si materials system — a fact not always appreciated in technology development planning. The adoption of a new gate dielectric candidate in the timeframe required by the industry roadmap (four to five years) will be an even greater challenge. A new generation of scientists and engineers will be challenged to not only integrate these new materials in time, but also to make use of the research and development progress of the past.

Robert M. Wallace is a professor of materials science and director of the new Laboratory for Electronic Devices and Materials at the University of North Texas. He formerly worked for Texas Instruments, most recently leading a research team in TI's Central Research Laboratories that focused on advanced device concepts and material integration issues. He has a Ph.D. in physics from the University of Pittsburgh.
e-mail: rwallace@unt.edu

Glen D. Wilkis a technical staff member in the Electronic Device Research Laboratory at Agere Systems (formerly Lucent Technologies' Bell Laboratories). He specializes in advanced CMOS device integration as well as materials for high-speed and optoelectronic devices, and previously worked at TI's Central Research Labs. He has a Ph.D. in applied physics from Harvard University (Cambridge, Mass.).
e-mail: gwilk@agere.com

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Acknowledgements

Robert Wallace acknowledges the support of the Texas Advanced Technology Program and the Semiconductor Research Corp. in the preparation of this series.