Direct CMP for STI

		At a Glance
	The planarization process for shallow trench isolation (STI) structures requires substantially better process control than is needed for tungsten plug and interlevel dielectric (ILD) CMP. In CMP, the material removal rate depends on both feature size and pattern density. In STI processes, engineers typically compensate for pattern density variations by adding more process masking steps and dummy features. A direct STI CMP process eliminates these extra steps, thereby reducing process complexity, improving productivity and lowering cost of ownership.

Shallow trench isolation (STI) has become an enabling technology for sub-250 nm devices¹ because of its higher packing density² and better planarity relative to the local oxidation of silicon (LOCOS) approach. In the STI process, isolation trenches are plasma etched in the silicon using a silicon nitride etch mask, and then overfilled with CVD silicon dioxide. Next, the oxide is polished back to a planar surface using CMP, while removing as little of the nitride as possible. Finally, the nitride is chemically etched to the silicon surface, and active devices are fabricated in the exposed silicon regions.

STI achieves better scaling and isolation between transistors, and allows smaller channel-width encroachment, better planarity and superior latch-up immunity. However, these advantages come at the expense of increased process complexity, including the requirement for well-controlled CMP.

STI CMP requirements

One of the greatest challenges in STI CMP involves achieving planarization uniformity over both the die level and the wafer level. Uniformity requirements vary with device and application, but typically the thickness uniformity across the wafer (usually called within-wafer nonuniformity, or WIWNU) must be <3%. Erosion of the trench oxide (dishing) must typically be <20-50 nm. The conflicting process requirements of STI CMP result in a much narrower process window.

The STI CMP process ideally stops polishing at the nitride mask layer. However, oxide removal is faster than nitride removal, easily leading to oxide dishing in the trenches. To minimize dishing, the silicon dioxide polish should be stopped as soon as the oxide over the nitride clears.

Accordingly, the quality of an STI process is measured by the control of trench oxide and nitride thickness. This requires tight control of the step height between the trench oxide surface and silicon surface after nitride strip (D S), as shown in Figure 1.

It is advantageous to have a positive D S, which helps eliminate the reverse narrow channel effect that causes sub-threshold leakage (a low current flow that occurs when the transistor is in the off state). Both the average value and range of DS should meet certain specifications across all features and all circuits. The specification for D S depends on the device type, and can be in the range of 50-100 nm.

The polishing rate during STI CMP depends on feature size, pattern density and the CVD oxide process. Two types of plasma CVD gap-fill processes are typically used: plasma-enhanced CVD from TEOS and high-density plasma CVD (HDPCVD). Figure 2 shows both post-deposition profiles. During HDPCVD, sputtering by ion bombardment forms cusps on the surface over narrow nitride features. The thickness of the oxide depends on this nitride feature width. Atmospheric-pressure or low-pressure thermal CVD can also be used, producing other topographies. STI CMP must be able to adapt to all CVD gap-fill processes.

	1. By maintaining a slightly positive D S, the step height between the trench oxide and silicon after nitride strip, the process engineer minimizes the chances of sub-threshold leakage caused by the reverse narrow channel effect.

Because of localized differences in polish pressure, small features polish faster than large features, and oxide in narrow gaps polishes slower than in wider gaps. Features of varying pattern densities on the chip typically lead to uneven clearing of oxide from the nitride (Fig. 3). Engineers commonly manage this problem by adding an extra process sequence prior to CMP called reverse mask etch-back (RME). After CVD oxide fill, the surface of the oxide over the active area is higher than the trench oxide. Masking the trench region and then etching back the exposed oxide over the active region reduces this height difference, thereby reducing the degree of incoming nonplanarity and allowing a wider CMP process window.

This RME sequence requires extra photolithography, etching and cleaning steps, which increase process complexity and cost. The masking step places additional tolerance and alignment demands on photolithography and increases fab cycle time.

2. The CMP process must address the topography profiles resulting from different CVD methods. For HDP oxide, step height depends on pattern density. (Note: not to scale.)

Since RME increases the design and mask set costs, there is a need for direct STI CMP processes for all device types, with a process window that accommodates a wider range of feature densities.

Direct STI

Direct STI requires greater control of the CMP process and less sensitivity to pattern density and feature size. Device makers are pursuing two different strategies to reduce pattern density variation. In the first approach, companies modify the chip layout design by adding dummy features, for example. However, in certain ASIC and mixed-signal device layouts, dummy features cannot be readily used, making direct STI CMP more difficult.

3. Feature size has a significant effect on oxide removal rate: faster in wider trenches and slowest over wide nitride features. (Note: not to scale.)

The second, and preferred, strategy is to improve the CMP process. The ultimate goal is to improve planarization capability to the point where RME masking layers and design alterations can be eliminated.

Lam has developed direct STI processes using its Teres CMP system with Linear Planarization Technology (LPT)³ and multi-zone air bearing platen (Fig. 4). During development, we identified the key parameters requiring control and their effects on direct CMP process results.

	4. Linear Planarization Technology provides polish profile control using radial tuning at multiple locations (see arrows) to improve process uniformity and enable direct STI CMP.

Figure 1 showed the basic planarization requirement for STI CMP. The CMP process margin is affected by several CMP process and hardware variables (Table). Integration issues such as trench etch-depth uniformity, oxide fill uniformity, and degree of overfill, will also affect the CMP process margin.

A successful STI CMP process must provide a means to control WIWNU and compensate for the incoming oxide profile, pattern density variations and wafer topography.⁴ It also should have endpoint detection capability.

On the Teres system, the wafer is held by a rotating spindle and pressed against a moving polishing belt. Downforce is applied via the spindle. The multi-zone platen also pushes the belt upward against the wafer using air pressure.

This system is uniquely designed to optimize WIWNU by compensating for radial nonuniformity profiles on incoming wafers. We characterized the removal rate vs. air pressure of each platen zone for each consumable set, including belt pad stack configuration and slurry parameters.

Factors Influencing Direct STI CMP Process Margin Using Linear Planarization Technology
CMP process metrics	Effect on DS	Effect on DS range	Process/hardware variables
Trench oxide dishing	Ö	Ö	Slurry chemistry and selectivity Pad surface asperity
Pattern density dependence and within-die range	Ö	Ö	Slurry chemistry Pad hardness Pad stack configuration Wafer nanotopography
Within-wafer nonuniformity	Ö	Ö	Slurry distribution Polishing head design Platen design Pad grooving
Wafer-to-wafer variation	Ö		Pad conditioning Head-to-head variation Tool stability
Targeting (endpoint)	Ö		Endpoint detection Endpoint resolution Pad surface structure
Overpolish sensitivity	Ö	Ö	Slurry chemistry

Based on a design-of-experiment (DOE) analysis of the air bearing responses, we constructed a mathematical model of the removal rate profile. This model is used to predict a set of process parameters that produce a removal profile, compensating for the deposition profile (Fig. 5).

	5. By optimizing the multiple air bearing pressure zones, one can match the removal profile to the incoming profile.
	6. Lower downforce and harder pad and belt materials provide better long-range (mm to cm) planarization. The study used an MIT Standard STI test mask to define the trench pattern. (Note: Thickness values are normalized.)
	7. Minimum pad conditioning gives the best planarity on 100 µm pitch features. The more trench oxide that remains for a given nitride thickness, the better the short-range planarity. The percentage of polish refers to the pad conditioning duty cycle. Trench oxide thicknesses were measured in the scribe line.

This capability is not easily achieved with a uniformity control scheme based on conventional rotary CMP tools that use a pneumatic carrier or active retaining ring control.

It was shown that low-downforce polishing provides better planarization than high-downforce CMP (Fig. 6). With lower downforce, the pad is less conformal to device topography. Normally a lower force reduces the material removal rate, but in this system the higher belt speed compensates for this effect, delivering good planarization and removal rates that are equivalent to other commercial systems.

Short-/long-range planarity

We found that the short-range planarity (sub-micron to 100 µm in length) is largely decoupled from long-range planarity (mm to cm scale). The short-range planarization is influenced by the slurry chemistry, the selectivity (ratio of the oxide-to-nitride removal rates) and the surface asperity (surface condition) of the polishing pad. Figure 7 shows the effect of pad conditioning on short-range planarization. A convenient metric for short-range planarization is the amount of remaining trench oxide for equal remaining nitride thickness.

Less pad conditioning results in a greater remaining trench oxide thickness. In other words, a smoother pad surface leads to better short-range planarity.

Long-range planarization strongly depends on pad hardness or rigidity and the pad stack configuration.⁴ The pads can have a single layer or dual layers with a softer backing. The polishing pads are attached to the linear belt, where the material determines pad rigidity. The belt can be relatively rigid stainless steel or a flexible polymer.

Figure 6 shows the effects of pad configuration, downforce and linear belt speed on planarization. The measure of long-range planarity is the average within-device range for the trench oxide thickness. Using a stainless steel belt backing, the hardest pad configuration — a single 50 mil thick IC-1000 pad directly on the S.S. belt — yielded better planarization length than softer stacked pads consisting of a 32 mil pad over a 50 mil softer pad or a 50 mil pad over a 50 mil softer pad.

A recently developed polymer polishing material in belt form was found to offer better planarization capability than the IC-stacked pad. The user can select the thickness of the polishing material to adjust long-range planarization (Fig. 6). An additional advantage of this new belt polishing material is a longer pad lifetime, which reduces consumable costs (Fig. 8).

Endpoint detection

Endpoint detection (EPD), widely used in CMP processing, can significantly reduce the variability of the CMP output for STI.

The most common method for STI endpoint is based on the analysis of the optical signal reflected from the wafer front surface, using either a single-wavelength laser or a broadband white light source. The multi-wavelength approach offers the ability to measure dielectric film thickness in situ and can achieve a high signal-to-noise ratio using algorithm-based signal processing. EPD technology minimizes wafer-to-wafer variation and reduces the likelihood of wafer rework during CMP.

Summary

	8. The polymer belt can deliver a <5% within-wafer nonuniformity. The pad wear rate is only 3 mil/1000 wafers for a 75 mil pad with 30 mil groove depth.

Direct STI processes can improve productivity and reduce costs. Enabling these processes requires tight control of short-range and long-range planarity during CMP. CMP process control can be improved by taking advantage of the uniformity tuning capabilities inherent in a CMP system.

On the system used in this work, controllable parameters that impact planarity include a multi-zone platen with controllable radial uniformity, and variable downforce and belt speed control that optimize removal rate independent of uniformity profile. We also recommend optimization of the pad stack and belt parameters. Robust endpointing capability further improves process control while maximizing yield.

Eugene Zhao is the consumables technology manager for the CMP/Clean Products Group of Lam Research Corp. Prior to joining Lam, he worked on CMP and cleaning process development at IBM Almaden Research Center and OnTrak Systems. He has a B.S. in chemistry from Fudan University (Shanghai, China) and a Ph.D. in physical chemistry from the University of California at Berkeley.
e-mail: eugene.zhao@lamrc.com

C. Shan Xuis the 300 mm technology manager for Lam's CMP/Cleaning Products Group and has worked on various CMP applications and consumables development. He received his Ph.D. in physical chemistry from the University of California at Berkeley.
e-mail: shan.xu@lamrc.com

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REFERENCES

1. L. Peters, "Choices and Challenges for Shallow Trench Isolation," Semiconductor International, April 1999.
   
2. C. Yu, et al, "Dishing Effects in a Chemical Mechanical Polishing Planarization Process for Advanced Trench Isolation," Appl. Phys. Letters, Vol. 61, 1992, p. 1344; I. Ali, et al, "Physical Characterization of Chemical Mechanical Planarized Surface for Trench Isolation," J. Electrochem. Soc., Vol. 142, 1995, p. 3088.
   
3. R. Jairath, et al, "Linear Planarization for CMP," Solid State Technology, October 1996, p.107; R. Jairath, et al, "Performance of Ontrak Systems' Linear Planarization Technology (LPT) for Dielectric CMP Processes," CMP-MIC, 1997, p. 194.
   
4. C.S. Xu, J. Liu, Y. Xia, "Quantitative Study of Chemical Mechanical Planarization Process Affected by Bare Silicon Wafer Front Surface Topography," J. Vac. Sci. Technol. B, Vol. 17, No. 5, 1999, p. 2210.