The Cost of Imperfect Wafer Environmental Control

Devon Kinkead and Jim Mastrobuono Extraction Systems Inc., Franklin, Mass. Kim Dean and Walt Trybula International SEMATECH, Austin, Texas -- Semiconductor International, 6/1/2001

• What are the bottom-line risks and rewards in a new technology production ramp?
• What is a contamination event, and how does an average event affect critical dimension control?
• What factors should be considered when evaluating the addition of process control and monitoring equipment during new process ramp-up?

In Part 1 of this two-part article, we provide a brief overview of issues related to chemically amplified resist contamination, and we explore the economics of timing and process control during ramp-up of new production technology. Part 2 discusses the implications of imperfect molecular base contamination control in advanced lithography and a number of return-on-investment scenarios for on-line contamination metrology equipment.

Chemically amplified resist contamination

Low k₁ factor 90 nm device production using 193 nm lithography will be the basis of advanced semiconductor production in the near term. At this technology node, the International Technology Roadmap for Semiconductors (ITRS) has established CD control budgets of 6 nm for MPU/ASIC devices, and 9 nm for memory (post-etch, 3 s). Alarmingly, these entire CD control budgets can be consumed by a lapse in wafer environmental control for molecular base contamination.

To understand this situation, we must keep in mind the fundamental change in photoresist chemical mechanisms demanded by the transition to DUV lithography. At 248 and 193 nm, chemically amplified resists are necessary because they can pattern finer features faster — that is, with less energy — than conventional resists.

Unfortunately, one important drawback of chemically amplified formulas is their sensitivity to base contaminants, which neutralize acid catalysts that provide secondary amplification of the photoreaction. A comprehensive discussion of contamination issues related to chemically amplified resists is available in C. Grant Willson's short course, Resists for DUV Lithography (Microlithography 99, SPIE); a condensed version has been published previously.¹ For the purposes of this discussion, the most salient points are:

• Base contaminants (such as ammonia, n-methyl pyrrolidone and trimethylamine) can permeate the resist polymer and change the quantum efficiency of the reaction at the resist's surface-to-air interface. This is manifested by a widening of the top of the image profile, commonly called a "T-top"; most DUV lithography equipment employs chemical filters to control the effects of environmental base contamination.
• Problems can also be caused by two other important effects of base contaminants: CD change resulting from acid diffusion, and substrate poisoning. These effects are more insidious because they can create systematic variation over time.
• Documented sources of base contaminants in fabs include ambient air, cross-contamination from process chemicals containing volatile molecular bases,² paint, ceiling tiles and volatile humidifier system boiler additives. More recently, researchers have discovered significant pollution from additional "hidden" sources, including gloves, caulk and the most significant source, people, who can continuously generate 70-3800 ppb of molecular base contamination.³

With this awareness of how molecular bases can disrupt the otherwise elegant process of chemically amplified resist pattern formation, we can turn our attention to the financial realities of device production and how contamination fits within that larger economic scheme.

The economics of delayed ramp

	1. Product volume peaks as the time approaches for introduction of the next product generation.

Delay in the startup of a new chipmaking facility or the introduction of a new product line can have serious consequences because of the semiconductor industry's relentless drive toward newer, faster, cheaper designs. While every specific situation has its own parameters that must be analyzed by individual companies, the basic outlines of the situation can be clearly generalized.

Figure 1 shows the price vs. time in service for DRAM devices (all data shown is from Dataquest reports in 2000 and 2001). The shape of the cost curve is one of decreasing cost over a relatively short time, followed by a short period of rapidly diminishing changes in cost, and finally a constant commodity price that is, perhaps, two orders of magnitude lower than the initial price. The cost curve is related to the volume shipment curve — product availability is scarce at the beginning, followed by a period of increasing availability, with the product volume peaking as the time approaches for introduction of the next product generation.

2. An organization that can provide higher-performance devices at any given time will realize higher revenues than its competitors.

Figure 2 depicts the price-vs.-time curve for leading-edge logic devices, with a couple of key products identified (this data is from both Dataquest and MicroDesign Research reports). The main point here is the decreasing time to obsolesce logic products. Consequently, the value of these products starts high and nose-dives within a period of months. Thus, there is a direct link between performance increases and economic benefits — an organization that can provide higher-performance devices at any given time will realize higher revenues than its competitors.

Note: Because of the specialized nature of ASIC products, product transition curves like those shown in Figure 1 and Figure 2 are extremely difficult to construct and require internal information about a company's specific product evolution. Therefore, details of the ASIC life cost curve are not presented. A manufacturer of these devices can perform its own analysis to determine its own market economics.

The broad outlines of this situation have been known for some time; recent studies^2,3 have quantified matters, and shown that the impact of a delayed introduction for DRAM has a financial consequence of $2.5M/day of delay.^4,5 This analysis considers competitive facilities that introduce a product, go through exactly the same learning curves, and have the same total volume capacity. Since wafer fabs tend to be built for specific capacities, such as 5000 wafer starts/week, this assumption is not unrealistic.

	3. The major consequence of delay is that the later products are produced, the less valuable they are.

Figure 3 shows the reason for this financial impact. The pricing curve (price received) starts high and diminishes rapidly, while the volume curve starts low and increases rapidly. The second volume curve depicts the exact same scenario for a competitive facility that begins production slightly later. The major consequence of delay: Products are less valuable the later they are produced. Company A has introduced its product first, at point A1, while company B is in production some time later (point B2).

Consider points A and B in Figure 3. At time t, company A is producing a certain volume of products (point A1) and receiving a value of point C1 for each unit. At a later time, company B starts producing (point B2), while company A is producing the volume indicated by point A2. Market forces dictate that both receive the same compensation for the products, which is indicated by price C2 multiplied by the respective volumes (A2 and B2). The different total value is strictly based on the volume they can provide to the market.

The late-ramping organization has all the same learning costs and yield improvements, but its payback is less because of the lower market prices at the time they can supply the products.

Because of the difference in the beginning of production, company A's facility achieves maximum capacity at point A3, while company B reaches maximum capacity at the later time represented by point B4. Had company B started earlier, it would have received higher value in the market.

The previously cited analysis, which compared revenue generated by the two firms over the period until both organizations were at full production, found A's advantage over B to be $2.5M/day of delay for B. This assumes that each organization had identical operating costs, with the only difference being revenue generated based on volume to market, which translates to net revenue. The point of note is that delay in product introduction causes huge revenue costs. Remember that this analysis was performed for the DRAM product cycle; the logic cycle can be even less forgiving.

The value of shifting the mean

Having considered the question of timing, we can now turn our attention to another major factor in ramp-ups: process control.

Semiconductor production is a mass manufacturing process — many devices are manufactured on each wafer, with numerous wafers in a lot. With more than 500 individual process steps on a leading-edge product, the potential for intra-wafer and intra-lot variability is substantial. If process variation impacts certain critical parameters, the product's value can be reduced — a 1.5 GHz microprocessor will bring one price while a 1.3 GHz processor will bring substantially less, with process control a key factor in operating speed.

	4. The distribution of product output (binning) based on frequency for a hypothetical processor is shown.

Figure 4 depicts the distribution of product output (binning) based on frequency for a hypothetical processor. Improved process control shifts the mean of the binning to the right (higher frequencies), which correlates to more availability of the more desirable products, and higher revenues for the same silicon.

There are revenue impacts that can be ascribed to the improvement in binning. These will be different for each company, but a generalized equation can demonstrate the revenue advantage from improved binning. The variables are the number of die per wafer, the cost advantage per nanometer of improved control, and cost of the improved control as a function of the total volume (in this case the total volume could be amortized across several product lines if the facility has multiple products).

The equation can be stated as:

RE = TP * CAN / (COI/TP)

Where:

• RE is the realized economic benefit per die.
• TP is the total product or total number of die (die per wafer × the number of wafers).
• CAN is the cost advantage per nanometer of CD.
• COI is the cost of implementation, which includes operating costs and depreciation.

A hypothetical example: Assume that a product is produced with 100 devices/wafer, the total product volume is 1 million units, and the average unit price is $200. If a 1 nm improvement in control improves the product value by $5, the gain is $5M. The ability to determine the justification of a process improvement can be easily calculated.

Conclusions

Taking the timing and process control issues together, we have a framework for examining the impact of faster learning curves and improved yields during initial delivery of a product. Based on the information presented, semiconductor manufacturers can gain demonstrable bottom-line advantages by expediting ramp-up while maintaining process control.

The individual impact is dependent on the product, market demand, timing and corporate-specific variables. Therefore, a detailed calculation of the benefit of a more rapid learning curve during ramp is left for the reader. However, it is clear that at ~$2.5M/day in ramp delay costs, and $5M/nm of CD variation, this is a high stakes business.

In our next installment (see Semiconductor International, July 2001 ), we will use this economic context to analyze the frequency, impact and cost of imperfect molecular base contamination control in the 90 nm technology node.

Devon Kinkead, a founder of Extraction, has several years of experience as project manager of AMC control projects on process tools and cleanrooms in fabs, as well as many other industrial applications worldwide. He has a bachelor's degree in biology/chemistry from The Claremont Colleges (Claremont, Calif.).
Phone: 1-508-553-3900
e-mail: dkinkead@extractionsystemsinc.com

James Mastrobuonorecently joined Extraction as the corporate quality director. He holds a B.S. in chemistry from Gannon University (Erie, Penn.) and an M.A. in environmental studies from Brown University (Providence, R.I.).
Phone: 1-508-553-3900
jmastrobuono@extractionsystemsinc.com

Walt Trybulais an International SEMATECH Senior Fellow in the lithography division. He has a Ph.D. in information science from the University of Texas (Austin), an M.B.A. from James Madison University (Harrisonburg, Va.) and a B.S. in physics from the Illinois Institute of Technology (Chicago).
Phone: 1-512-356-3000
e-mail: walt.trybula@sematech.org

Kim R. Deanis project manager of the 157 nm resist development group at International SEMATECH. She received her Ph.D. in physical chemistry from the University of Texas (Austin) in 1990 for her research in the photophysical properties of polymers.
Phone: 1-512-356-3000
e-mail: kim.dean@sematech.org

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REFERENCES

1. Devon Kinkead, Monique Ercken, "Fine Lines Between Success and Failure," European Semiconductor, May 2000, p. 19.
   
2. Chemical Safety Handbook for Semiconductor/Electronics Industry, second edition, OEM Press, Beverly, Mass., 1998.
   
3. Carl Larson, Oleg P. Kishkovich, "Amine Control for DUV Lithography: Identifying 'Hidden' Sources," Solid State Technology, Contamination Control supplement, May 2000, p. S5.
   
4. Walter Trybula, "Technology Acceleration and the Economics of Lithography," International Forum on Semiconductor Technology, Antwerp, Belgium, March 2001.
   
5. Walter Trybula, Roger Bohn, "The Strange Economics of Semiconductor Product Manufacturing," in preparation.
   

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