Sematech 3-D Program Provides Lessons
Sematech's 3-D interconnect program has provided the equipment and materials industry with a proving ground over the last 18 months. Andy Rudack, a Sematech metrology engineer, noted that the bonded wafers exceed the SEMI standard for wafer thickness and weight, presenting a variety of readily solvable challenges.
David Lammers, News Editor -- Semiconductor International, 11/2/2009
Sematech's 3-D interconnect program has faced plenty of hands-on challenges over the last 18 months, many of them stemming from dealing with the non-standard thicknesses and weights of the bonded wafers, said Andy Rudack, a metrology engineer at the program based in Albany, N.Y.
When two 775 µm-thick wafers are bonded and later thinned, it creates challenges for robots, older FOUPs, wafer ports, edge trim tools, notch alignment and other portions of the fabrication chain. "Working with bonded wafers complicates the hardware," Rudack said in a 3-D "Lessons Learned" presentation at the ISMI Symposium, held in Austin, Texas recently.
Sematech's 3-D flow begins with creating vias on a 775 µm-thick wafer, which is then flipped upside down and glued to a carrier wafer, creating a 1550 µm-thick behemoth. The top wafer is thinned to 25 µm, leaving a more-manageable 800 µm-thick bonded wafer.
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Edge trimming can prevent peeling and edge chipping. (Source: Olympus-ITA) |
The 3-D development team has created a complete flow of equipment for 3-D fabrication at Sematech, and Rudack described the efforts required to make sure each tool was able to readily handle the non-standard wafer thicknesses. For example, the edge clip on a CMP tool had to be been redesigned to handle the 800 µm-thick bonded wafer pair.
Fabs must ensure that their robots are capable of handling the heavier wafers. "In most instances the wafer pairs did not exceed the maximum weight of the robot," he said. Edge trimming becomes an important step to protect against edge chipping, delamination and other problems. Voids between the bonded wafers can easily cause severe wafer bowing, he warned.
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Keeping the alignment notches on the two bonded wafers aligned presents a challenge. (Source: Olympus-ITA) |
Making sure the wafer index marks remain in place is important. "You have to be aware of which lots are bonded wafers." If wafer markings are preserved through the bonding and thinning steps, "you can track the wafer fairly reliably." The alignment notches must be preserved and carefully aligned, Rudack said.
If a tool has three load ports, one should be adjusted to handle the thicker wafers and dedicated to bonded wafers, he advised. While standard FOUPs, especially the newer designs, work fairly well, companies should avoid using the wafer shipping boxes, or FOSBs, with bonded wafers, he said.
SEMI has developed highly detailed standards for the 775 µm wafers, and much work is underway to update the standard for bonded wafers.
"There is an awful lot of SEMI activity now to deal with bonded wafer pairs, and where the standards need to be changed. Your specific tool set will be different from Sematech's but you should be able to shake out most of the problems specific to your process tools. We were able to make it work," he concluded.
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