IEDM Confronts Logic Scaling Challenges
The International Electron Devices Meeting (IEDM), set for Dec. 6-9 in Baltimore, includes presentations on new annealing techniques, FinFETs, compound semiconductors and random telegraph noise. The conference, with 215 paper presentations, will be preceded by a Sunday short course on scaling challenges organized by TSMC's Howard C.H. Wang.
David Lammers, News Editor -- Semiconductor International, 10/15/2009
While the 55th International Electron Devices Meeting (IEDM) takes a brief detour to Baltimore this year, the conference — arguably the premier event for semiconductor technologists — will maintain its focus on the challenges of device scaling.
The 2009 IEDM — scheduled for Dec. 6-9 at the Hilton Baltimore due to renovations this year at the normal venue for the East Coast IEDMs, the Washington Hilton and Towers — features a Tuesday evening panel session on technology elements for the 15 nm node and a daylong Sunday short course on scaling challenges, organized by Howard C.H. Wang of Taiwan Semiconductor Manufacturing Co. Ltd.
The Dec. 7-9 presentations include ~215 papers, roughly divided among logic, memory and emerging technologies such as printed electronics, graphene, biomedical devices and others.
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At IEDM, Intel will report on InGaAs QWFETs that include a TaSiO-InP dielectric. |
Among the logic papers, Intel Corp. researchers will continue their annual progress reports on InGaAs quantum-well field effect transistors (QWFETs), the subject of two previous IEDM papers. This year, the topic is a TaSiO-InP high-k dielectric integrated on a transistor with a 35 nm gate length. Intel claims the device has the highest reported drive current of 0.28mA/µm, and a peak transconductance of 1350 µS/µm, according to an abstract of the paper.
Researchers from Purdue University will describe etching techniques that reduced etch damage on an InGaAs FinFET transistor. While InGaAs transistors are among the fastest known, the material is susceptible to etch damage, which can lead to electron traps that degrade performance. The Purdue team created a damage-free dry/wet etching process, and used it to build the first reported InGaAs FinFETs. The tri-gate vertical transistors had channel lengths of ~100 nm and widths of ~40 nm, with no apparent short-channel effects.
At last year's IEDM, an IMEC group used full-field EUV lithography to fabricate dense contact holes in 0.186 µm2 SRAM cells made with FinFET transistors. This year, IMEC will present fully functional 0.099 µm2 6-T SRAM cells, with both contact holes and metallization layers created with EUV lithography, while 193 nm immersion scanners were employed to pattern the fins and gates. IMEC also used selective epitaxial growth with double spacers, ultrathin silicides and tungsten metallization to build the SRAM cells, which remained stable at 0.4 V operation.
Millisecond annealing techniques
A team of IMEC and Applied Materials researchers will describe using millisecond anneals to create thin silicides required for junction scaling, 6 nm gate length reduction, and >1 decade junction leakage reduction. The team claims that the silicide formation technique resulted in a significant yield improvement over conventional soak anneals, without transistor performance degradation.
Fujitsu Microelectronics researchers also studied the impact of millisecond annealing on device characteristics and SRAM yields. The team compared flash lamp annealing (FLA) and laser spike annealing (LSA), concluding that LSA is promising due to its lower pattern sensitivity and potential for performance enhancement. Hot spot generation with LSA can be avoided with active area size restriction, the Fujitsu team will report.
A group of Taiwan-based researchers will report on the use of a microwave dopant activation technique. The team — drawn from National Nano Device Laboratories, National Chiao Tung University, DSG Technologies Inc. and Dayeh University — created 65 nm CMOS TFTs with the technique. "We have successfully activated the poly-Si gate electrode and source/drain junctions at a low temperature of 320°C for only 100 s, which is promising for integrating high-performance upper layer nanoscaled transistors as required by low temperature 3-D IC fabrication," they said in an abstract of the paper.
Random telegraph noise worsening
As transistors become smaller, random telegraph noise (RTN) becomes a larger problem, and two Japan-based research teams take up RTN in ultrasmall devices. Broken atomic bonds near the channel can trap and release charge carriers, generating a discrete switching signal known as RTN that may interfere with the device's operation.
Working with 22 nm devices, researchers from Hitachi Ltd. and IBM Corp. measured Vt variations caused by RTN and others caused by random dopant fluctuations. They observed that with proper annealing of the devices, the variations from RTN will not exceed those caused by random dopant fluctuations. At the 15 nm node, however, RTN will be a severe reliability problem, more challenging that random dopant fluctuations.
NEC Electronics also studied 22 nm devices to come up with a new analysis method for understanding RTN waveforms and statistical behavior. The team measured multiple samples, and proposed two methods for a comprehensive understanding of RTN: a time-lag plot approach and a model-based statistical parameter extraction scheme.
Silicon-on-insulator advances
Fully depleted SOI is also on the IEDM agenda. An IBM team will report results from highly scaled devices fabricated on extremely thin SOI (ETSOI) CMOS, with silicon carbon (SiC) stress techniques. The IBM team claims record low variability for low-power system-on-a-chip applications.
A Leti-Soitec-STMicroelectronics team will report on a hybrid fully depleted SOI/bulk high-k/metal gate platform for LP multimedia applications. The Grenoble-based team will report ring oscillator delay improvements of ~15% compared with bulk 45 nm devices.
An IEDM paper given by researchers from the Indian Institute of Technology-Bombay and Infineon Technologies will compare simulated results from planar and non-planar SOI devices. "Non-planar devices perform poorly in comparison to ultrathin body (UTB) planar SOI MOSFETs, and are not the ideal choice for SoC applications," the paper's abstract concludes.
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Not missing much by missing IEDM.
not missing much - 10/16/2009 11:37:26 AM CDT
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