IBM Readies 32 nm eDRAM With Low Latency
IBM unveiled a 32 nm SOI embedded DRAM, and will provide details at the upcoming IEDM in December. Gary Patton, vice president for IBM's SRDC, said the SOI eDRAM has latency and cycle times of <2 ns, uses 4× less standby power, and has "up to a 1000x lower soft-error rate (SER), better power savings, and reliability comparable to a similar SRAM."
David Lammers, News Editor -- Semiconductor International, 9/18/2009
IBM Corp.'s Semiconductor Research and Development Center (SRDC, East Fishkill, N.Y.) has fabricated a 16-Mb embedded DRAM (eDRAM) test chip in 32 nm silicon-on-insulator (SOI) technology. The eDRAM has a <2 ns access time, and is 4× as dense as "any comparable 32 nm embedded SRAM in the industry," IBM said.
 |
|
IBM will detail its 32 nm SOI-based eDRAM technology at the upcoming IEDM in Baltimore. |
The eDRAM is fully compatible with logic transistors, with no degradation in logic performance. It incorporates a deep trench capacitor structure, with a high-k dielectric and metal liner capacitor technology. IBM will detail the 32 nm eDRAM at the International Electron Devices Meeting (IEDM), planned for Dec. 7-9 in Baltimore.
Gary Patton, vice president for IBM's SRDC, said the SOI eDRAM has latency and cycle times of <2 ns, uses 4× less standby power, and has "up to a 1000× lower soft-error rate (SER), better power savings, and reliability comparable to a similar SRAM."
Besides using the SOI eDRAM for use in its own products, IBM is offering it now to early-access foundry customers. IBM is working with ARM Ltd.'s design division to incorporate it in their 32 nm library; an initial 32 nm ARM library is available now. IBM said it is working with ARM now on 22 nm SOI technology, "enabling ARM to gain early access to this technology."
IBM claims the eDRAM cell is twice as dense as any announced 22 nm embedded SRAM cell — including the 22 nm SRAM announced by IBM in August 2008 and claimed to be the world's smallest.
"We are making this 32 nm offering available to clients," Patton said, adding that it marks "a clear progression path" to 22 nm SOI technology. Besides servers, the eDRAM is targeted at printers, storage and networking applications, as well as for low-power mobile, consumer, and game systems.
Power 7 L3 Cache
IBM is incorporating the eDRAM in the 45 nm Power 7 server processor, said IBM spokesman Jeff Couture. IBM discussed Power 7, IBM's flagship MPU, at the Hot Chips conference held in Palo Alto, Calif. last August. With up to eight cores per-chip, each core operates at 32 gigaflops, and is fed by SRAM and the on-board eDRAM acting as the L3 cache.
Nathan Brookwood, a microprocessor analyst at Insight 64 (Saratoga, Calif.), said IBM has many Power 7-based servers running at its IBM Austin Laboratory (Austin, Texas), where most of the Power development work is done. Power 7 servers are expected to begin shipping next year, with the high-end Power 595 server incorporating 64 processors.
The Power 7 core has 32 Mb of L3 cache on board, the first implementation of the SOI eDRAM. Brookwood said such a large L3 cache will make it possible for many applications to run entirely on-chip, without the bus delays associated with moving off-chip. "Any time you can quadruple the density of the cache without increasing the area, that is a significant advantage. And you can assume they can double the size of the cache when they move from 45 nm to 32 nm," he said.
Large caches also have become more important as MPUs have gone to multi-core architectures, where maintaining cache coherency is particularly challenging.
The eDRAM is just the latest example, Brookwood said, of IBM's "admirable job" at improving the technology it brings to the Power MPU series. "For the past eight years, ever since the introduction of the Power 4, IBM has been running like clockwork, something that I expect to continue with the launch of the Power 7 next year."
GlobalFoundries also has SOI eDRAM technology on its roadmap, raising the question of when Advanced Micro Devices Inc. (AMD, Sunnyvale, Calif.) will bring the technology on to its processors.
IBM@45: eDRAM, Si! High-k, No
06/27/2008IBM And The All-In Bet on High-K
10/06/2008IBM Offers 45 nm SOI Foundry Solution
02/09/2010Dual Liner Stresses NMOS and PMOS
12/31/2004
VIEW ALL PODCASTS
