Intel Ramping 32 nm Manufacturing in Oregon
Intel is shipping "large numbers" of 32 nm samples of its Westmere processor to PC vendors for system testing, said Intel Senior Fellow Mark Bohr. "The 32 nm process is certified, and we are loading up our first factory in support of planned Q4 revenue production," he said.
David Lammers, News Editor -- Semiconductor International, 9/14/2009
Intel Corp. (Santa Clara, Calif.) is "loading up its factory" — the D1D fab in Hillsboro, Ore. — with samples of the 32 nm Westmere processor, said Intel Senior Fellow Mark Bohr.
In a briefing prior to next week's Intel Developer Forum (IDF) in San Francisco, Bohr said Intel is "shipping large numbers of 32 nm samples to customers, who are engaged in major testing of their computer systems. The 32 nm process is certified, and we are loading up our first factory in support of planned Q4 revenue production."
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Westmere, Intel's first 32 nm processor, was demonstrated in January 2009. |
Production at D1D will be followed by the D1C fab in Hillsboro in the fourth quarter, followed by high-volume manufacturing at Fab 32 in Chandler, Ariz., and at Fab 11x in Rio Rancho, N.M. Intel has committed to spending ~$7B in support of the 32 nm rampup, Bohr noted.
Details of the 32 nm process, including the exact drive current measurements, the germanium content in the PMOS stressors, and other metrics, will be discussed at the upcoming International Electron Devices Meeting (IEDM), planned for Dec. 7-9 in Baltimore. Paul Packen, senior device group leader for the 32 nm CPU process, will discuss the 32 nm CPU process, and Chia-hong Jen will present on the 32 nm system-on-a-chip (SoC) process.
The time gap between the CPU and SoC processes is shrinking, to an expected six months for the 32 nm generation, Bohr said. At the 45 nm node, the SoC process lagged the CPU process by a year. At 22 nm, Intel hopes to cut the gap to three months, Bohr said.
Intel shrunk the pitch by 0.7× to 112.5 nm, as measured from the center of one contact to the center of the next contact. Although scaling the pitch shows that Moore's Law remains intact, Bohr said, "we are no longer in an era where simply scaling the transistor dimension is adequate. At each node we have to bring in other technologies and materials." At the 90 and 65 nm nodes, performance gains came largely from straining the silicon channel. At the 45 and 32 nm generations, the high-k/metal gate process led the way.
The replacement gate flow first involves creating the source-drain structures, including the SiGe stressors for the PMOS, and then etching away the sacrificial poly gate and replacing it with the metal gate. "The act of etching away the poly gate allows the channel to compress more" in the PMOS transistor, Bohr said. The result is PMOS drive currents that are getting closer to NMOS performance for Intel, Bohr said.
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PMOS drive currents are getting closer to traditionally faster NMOS devices. (Source: Intel) |
Although higher strain levels eventually will lead to higher defect rates in the channel lattice, Bohr said, "we have definitely not exhausted" the potential of strained silicon yet. The result has been a shrinking gap between PMOS and NMOS performance, another topic that Intel will explain in greater detail at the IEDM meeting, he said.
Intel's first use of immersion 193 nm lithography comes at the 32 nm generation. Bohr said immersion will continue to serve Intel's needs at the 22 nm generation. Asked if EUV lithography will be ready for the 15 nm generation, Bohr said, "It is not looking like EUV will will be ready, at least initially, for 15 nm production." He added that the company is working on techniques to extend immersion 193 nm lithography to the 15 nm generation.
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