GlobalFoundries Outlines 22 nm Roadmap
GlobalFoundries plans to introduce embedded silicon carbon (eSiC) to strain the nFET transistors at the 22 nm node, said John Pellerin, director of technology development. Through-silicon vias also are on the roadmap, but air gaps are not, Pellerin said prior to the groundbreaking ceremony of Fab 2 in Malta, N.Y.
David Lammers, News Editor -- Semiconductor International, 7/28/2009
GlobalFoundries (Sunnyvale, Calif.) plans to apply embedded silicon carbon (eSiC) stressors on its 22 nm nFET transistors, and is likely to use through-silicon vias (TSVs) to connect a fast SOI-based DRAM layer to a logic die, said John Pellerin, director of technology development at the IBM/GlobalFoundries Alliance in Fishkill, N.Y.
In an interview prior to last week's groundbreaking ceremony for the GlobalFoundries Fab 2 in Malta, N.Y., Pellerin said GlobalFoundries and its Fishkill partners, including Applied Materials Inc. (Santa Clara, Calif.), have largely solved the technical challenges of eSiC stressors. By moving to an in situ phosphorous doping scheme for the grown stressor layers, the researchers are able to stabilize the carbon atoms and sharply improve carrier mobility and drive current, he said.
At SEMICON West, Applied Materials touted its role in eSiC development with GlobalFoundries, including a new cleaning module for its deposition tool.
The move to TSVs is built upon IBM's work in developing an embedded DRAM in an SOI substrate. Pellerin said the SOI eDRAM has a fast access time but a relatively short retention time, requiring frequent refresh cycles.
GlobalFoundries is unlikely to introduce air gaps — a technology that IBM developed based on self-assembling polymers — in the interconnect dielectric at the 22 nm generation. "What we have found is that air gaps require cladding layers which reduce the benefits," Pellerin said. "Instead, we have developed cleaning and other techniques" that improve interconnect performance. By introducing pores to the low-k dielectrics at the 32 nm node, GlobalFoundries is able to reduce the k value to 2.4 from today's 3.0, he said.
Pellerin also said that GlobalFoundries is no longer pursuing the one-transistor ZRAM developed by Innovative Silicon Inc. (ISI, Lausanne, Switzerland), a capacitor-less design based on SOI substrates. Instead, GlobalFoundries is working on a thyristor-based memory with T-RAM Semiconductor Inc. (Milpitas, Calif.). GlobalFoundries and T-RAM announced in mid-May that GlobalFoundries would co-develop 32 and 22 nm versions of the T-RAM, which is based on SOI technology, for low-power cache applications.
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By doing collaborative R&D with IBM at CNSE in Albany, N.Y., GlobalFoundries intends to close the process technology gap with Intel Corp. |
The advances on the company's 22 nm generation roadmap come as GlobalFoundries executives say they plan to catch up with Intel Corp. in terms of new process technology introductions. Intel executives told industry analysts at SEMICON West that it plans to begin 32 nm production late this year.
At the Fab 2 groundbreaking last week, Tom Sonderman, vice president of manufacturing systems technology, told reporters that GlobalFoundries "is closing the gap with Intel" on leading-edge technology introductions. "By going to a shared technology development model with IBM," he said, "we are closing the gap. We were a year behind Intel at the 45 nm node, and that difference will be cut significantly at the 32 nm generation. By 22 nm, there will be no difference. It will be in the noise level."
The 300 mm fab at Malta is scheduled to begin 28 nm bulk production for foundry customers in late 2012, and then move to 22 nm SOI technology, producing AMD's microprocessors, including a Fusion product that will combine an MPU and a GPU in 22 nm SOI technology. GlobalFoundries also will have an SOI manufacturing capability at Module 1 of Fab 1, in Dresden, Germany.
Fab 2 in New York will be a two-level building rather than the conventional three levels, Sonderman said, with all of the wafer production on the upper floor, along with maintenance shops nearby the tools. A "zero footprint storage" approach will put some wafer stockers above the tools. Implant will be located off of the main waffle slab, reducing construction costs.
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IBM and GlobalFoundries (GF) executives recognizing that they were a year behind Intel at the 45 nm node have presented a very aggressive and risky 22 nm development roadmap in order to catch up with Intel. The 22 nm roadmap is to skip the 45 nm and go directly to the bulk 32/28 nm with high-K, but with no embedded silicon germanium (eSi-Ge) or nitride stress liners for n and p FETs. The 28 nm is linear shrink from the 32 nm just using the litho. Two reasons for not using the stressors are given; the effectiveness of stress layers degrades as device shrinks, and the cost saving. However, no comparative performance data such as Ion/Ioff with stressor vs no stressor is shown. IBM claims that its customers will be able to jump directly to the bulk 28 nm from today’s 65 and 45nm nodes. However, it will be highly risky directly to go to volume manufacturing of the new bulk 28 nm from the old 65 nm PD(partially depleted)SOI without the prior learning or experience in the volume manufacturing of the previous technology nodes such as bulk 45 and 35 nm. IBM has a lot of experience in high volume manufacturing of SOI technology such as 90 and 65 nm nodes, but practically no volume manufacturing experience in the scaled bulk technology for a long time. IBM plans to begin the bulk 32 nm production in the second half of this year. This is about the same time the publically announced Intel’s 32 nm production. Intel utilizes stressors for both n and p FETs to boost the mobility resulting in the Ion/Ioff of 1.62 ma/um and 1.38 ma/um for n and p FET, respectively at Ioff = 100 na and Vdd = 1 V. No Ion/Ioff data on GF’s 32 nm is reported. Therefore, the transistor performance comparison can not be made. Whether GF will be able to meet the production schedule and match the Intel’s transistor performance will not be known until such data is reported. The bulk 28 nm production is in the second half of 2010. As for 22 nm, GF plans to apply embedded Silicon Carbide stressor (e-SiC) on its SOI n-FET. This is not expected because one of the reasons not using eSiGe for p-FET and nitride liner for n-FET is the ineffectiveness of stress layers for scaled device, contradicting the 22 nm node. The 22 nm SOI production will be the same as the bulk 28 production, the second half of 2010. This is a very aggressive 22 nm production schedule. Intel has not announced its 22 nm transistor make-up and production date yet.
sang kim - 8/11/2009 10:48:30 AM CDT -
I salute GF's race to be the leading edge, but as a naturally much smaller company, it may make more sense to beef up trailing edge business, where there is more maturity, and access to more customers.
guest - 7/31/2009 9:54:21 AM CDT
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