Optical Lithography Is Still the Technology to Beat
Although EUV lithography is widely considered the prime candidate for post-optical lithography, the only available option to support 15 nm logic development in 2011-2012 is 193 nm immersion lithography with pitch division, said Yan Borodovsky, Intel's director of advanced lithography.
Aaron Hand, Executive Editor, Electronic Media -- Semiconductor International, 7/24/2009
Looking for answers about what lithography technology will take over critical layers beyond optical lithography, extreme ultraviolet (EUV) is widely considered the technology to beat. But looked at from a slightly different perspective, optical lithography is the technology to beat. No matter how many times technologists decry its impending doom, a seemingly unending stream of innovation has extended optical lithography well beyond what most believed was possible.
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Yan Borodovsky, Intel Senior Fellow |
Yan Borodovsky, Intel Senior Fellow and director of advanced lithography for Intel's Technology and Manufacturing Group, presented an overview of the situation at SEMICON West last week, challenging the speakers in the remainder of the session to show how other technologies will overcome barriers of cost, defectivity and readiness. Borodovsky and others were part of a lithography session at Wednesday afternoon's Device Scaling TechXPOT, exploring lithography challenges and solutions at 22 nm half-pitch.
The point of it all, of course, is to continue along Moore's Law to make smaller, cheaper chips packed with functionality. Borodovsky showed, by way of example, an Intel Atom dual-core processor that has 47 million transistors. Using 45 nm node technology, the chip, hardly larger than a grain of rice, still relies on 193 nm dry optical lithography for its most critical layers. "It still blows me away every time I think about it," Borodovsky said.
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| Intel's dual-core Atom processor, with 47 million transistors, is hardly bigger than a grain of rice. And it's printed with 45 nm logic technology and 193 nm dry lithography. |
The next stage, which memory manufacturers have already reached, is 193 nm immersion lithography. For Intel, "32 nm is our first dive into immersion litho, so to speak," Borodovsky said, refusing to say much about what the chipmaker's plans will be at 22 nm, development of which is in full swing for 2011 high-volume manufacturing. The numerical apertures (NAs) have gone as high as they can go at the current wavelength, and EUV lithography is looking like it won't be ready for the 22 nm node, so chipmakers have conceded that they will likely use some form of double patterning to bridge the gap from 193i to EUV.
But for the time being, 193 nm optical is the answer. "Because it's the only technology available to us, it wins," Borodovosky said. 193i is the only high-volume manufacturing option that's worthy of printing critical layers during 2009-2010 development, he said. Advancements in tooling, computational lithography, materials and maskmaking have made it possible to pattern logic with single-exposure optical lithography with k1~0.30 for 0.50× area density scaling, he added. But 22 nm will be the last logic node where most of the critical layers will be patterned with single-exposure 193 nm lithography, he said.
According to Borodovsky, 193i with pitch division is the only option available in 2009 and 2010 to support patterning for 15 nm logic design rule definition for 2011-2012 development. Although he acknowledged concerns with the cost of doing pitch division, he said those concerns were secondary, with the first order of business being capability. "We don't do 193 because it's cheap and easy to do," he said, noting that double patterning will be used if it's what can get the job done.
While others are working out how to make EUV, e-beam, nanoimprint or other lithography technologies truly viable, engineers will still be plugging away at making optical lithography continue to get the job done. So experts from several different camps spent the next two hours of the lithography session detailing and addressing the challenges facing key technology choices. As Borodovsky noted, all parts of the candidate replacement technology must be available, have equal or lower defect levels and significantly better die cost to offset the large risks of a new technology introduction.
Since the opportunity for Intel's 15 nm node 193i replacement for high-volume manufacturing will close by the end of 2011, assuming a 12-18 month lead time for high-volume orders, Borodovsky discounted e-beam's eligibility. "I have not seen any roadmap where direct write will be commercialized before 2011," he said. "So it will be out of the running."
The case for EUV
Borodovsky said his bet is on EUV lithography rather than nanoimprint because EUV can serve both logic and memory makers. However, it will be necessary to close all gaps in EUV maskmaking, mask storage and mask transport for defect-free (<0.003/cm2), pellicle-free patterning to enable 2011 orders for logic manufacturing in 2013.
Bruno La Fontaine, Lithography Fellow and program manager for lithography tools and new technologies at GlobalFoundries, made the case for EUV lithography. Although EUV is certainly not ready yet, he said, it's one of only two options (the other being double patterning) that have tools available to "exercise this equipment." GlobalFoundries, within the IBM Alliance, has access to one of ASML's EUV lithography demo tools at Albany NanoTech, where researchers have gotten real-world learning on mask defectivity, which is a key remaining concern for EUV lithography.
In fact, where the group expected to see hundreds of defects, they found only a relative few, and even fewer were found to be electrically critical, La Fontaine said. "It looks like we can do fairly high yield with EUV already," he added.
Although La Fontaine held back some results, promising more information at the EUVL Symposium in October, he noted that the team has recently been able to repeat past experiments with new state-of-the-art mask blanks, as well as state-of-the-art metrology, and defectivity was at least 100× lower than previously thought.
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| Initial results of EUV research done at Albany NanoTech show encouraging results, with only 1-3% of blank defects found to be printable on the wafer with 70-90 nm CDs (left), and ~10% of blank defects found to be printable with 45-60 nm CDs (right). |
To be a viable solution, EUV lithography will also need to bring cost down to less than it is for double patterning, La Fontaine said. To do this, it needs a throughput of >60 wph, an initial mask price <2× 193i masks, and a scanner price comparable to that of a 193i double patterning tool. High-power sources are the key to throughput, and La Fontaine expressed confidence that power will soon reach 100 W IF to achieve 60 wph. "I think by early next year, we should be where we want to be for source introduction," he said.
Bryan Rice, director of lithography at Sematech, discussed EUV from an infrastructure perspective, noting that mask blank defectivity is the most serious roadblock to EUV readiness. He said the yield gap is >25× for pilot production, and >100× for high-volume manufacturing.
Sematech is working on source and resist issues, but the main focus is on mask defects, working to fund the EUV mask metrology infrastructure. Sematech plans to build the three tools needed for critical metrology needs — actinic blank inspection, aerial image defect review, and patterned mask inspection for sub-22 nm capability — and help the industry to commercialize those solutions. Rice said that he is confident that by the EUVL Symposium in October they will have the commercial support that they need.
Other presentations rounding out the session included arguments from Ben Eynon, vice president of semiconductor business development at Molecular Imprints Inc., about the viability of nanoimprint lithography. Extending optical lithography further was explored by Matt Colburn, manager of advanced lithography at IBM, who gave an excellent assessment of double patterning; and Steve Renwick, principal engineer at Nikon Precision, exploring advanced imaging solutions for shrinking the k1 gap. Venkat Nagaswami, patterning technology director at KLA-Tencor, detailed current-technology metrology challenges. You can download all of the session's presentations from the SEMICON West website.
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It is often cited that EUV with its high k1, makes for easier, cheaper lithography. This would theoretically be true if we considered an all EUV lithography line, but in actuality fabs will continue using 193 nm immersion tools, at low k1, for at least some lower metal and via layers. The layout restrictions from the low k1 of these 193i layers will carry over to the critical front end layers. So even though the high k1 design freedom opportunity is there, it is wasted. Furthermore, the coexistence of two vastly different (EUV, 193i) infrastructures makes the cost advantage of EUV very unconvincing.
unconvinced - 9/29/2009 8:19:07 AM CDT -
Earlier this year Samsung started 4x nm DRAM for DDR3, which has to be with double patterning and immersion. Is it losing money this way, with its planned DDR3 DIMM product lines? If not, I don't see a reason for it to continue EUV support.
see softpedia - 9/25/2009 12:04:34 PM CDT -
Intel is self-contradictory on EUV use for 22 nm and beyond. A calculation by Intel's Components Research for IEUVI workshop in 2008 showed that even for 22 nm logic contacts, the shot noise would be extremely large (>10%). So it makes sense for them to consider alternatives like nanoimprint or maskless e-beam but they shouldn't be insisting on EUV as the preferred choice anymore.
looking at alternatives - 8/12/2009 6:36:19 AM CDT -
Well see p. 23 and 28, only 193i extended by pitch division is not shown as "High" cost but as "moderate". That goes against the main selling point of going to alternative NGL like EUV or NIL!
guest - 7/29/2009 6:54:23 AM CDT -
Yeah, it looks that way to me, too. In fairness, Intel has put an awful lot of money toward EUV over the years. But now they seem to be saying that they'd like to have it, and will use it if it comes, but if it doesn't, they'll use what's available. Am I off-base on that assessment?
Aaron Hand - 7/28/2009 11:04:39 AM CDT
NGL: Forever Next-Generation?
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