ST-Ericsson Taking 3-D to Mobile Phones
ST-Ericsson has a roadmap for commercial wireless products that includes what could be the first true 3-D ICs using TSVs. The memory-logic stack also will move to 3-D interconnects, driven by "the increased bandwidth required by the final application," said Yan Guillou, an ST-Ericsson manager.
Phillip Garrou, Consultant, Microelectronics Consultants of North Carolina, Research Triangle Park, N.C. -- Semiconductor International, 7/9/2009
ST-Ericsson has a roadmap for commercial wireless products that includes what could be the first true 3-D ICs using through-silicon vias (TSVs), arriving in 2012, said Yan Guillou, a senior manager at the wireless multimedia division of ST-Ericsson (Geneva).
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ST's CIS is in full production with TSV 3-D interconnects. |
Speaking at the European Microelectronics & Packaging Conference (EMPC), held last month in Rimini, Italy, Guillou outlined the advantages of 3-D technology for mobile phone applications. STMicroelectronics has pioneered the approach, being in full production of a TSV-enabled CMOS image sensor, and Guillou said much more 3-D integration is being planned by ST-Ericsson.
"Partitioning of chips with IP will appear," Guillou said. "A smart split of functions will be done in order to achieve the right cost/performance trade-off with TSV as the new enabler. An intermediate step based on a silicon interposer for the bottom die, containing only routing and few functions, is likely to happen."
The memory-logic stack also will move to 3-D interconnects, driven by "the increased bandwidth required by the final application," he said. "With a new memory-logic interface architecture, based on a wide I/O approach, the [application] bandwidth challenge might be overcome."
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ST-Ericsson has a roadmap for commercial wireless products. |
"This new wide I/O interface with parallel access to the memory will enable lower power consumption in the memory bus," Guillou said. "For cellular phones, this bandwidth bottleneck is foreseen after the low-power DDR2 memory generation."
Guillou said an issue with the wide I/O memory is standardization of the supply chain. "Since memory and logic die will come from different companies, standardization will be required to enable the OEM integrator to source, or double source, different memory types." Discussions are on-going between "major players" at this time to achieve standardization.
STMicro 3-D IC demonstrator
STMicro has built and tested a 3-D IC demonstrator consisting of a stack of 45 nm and 130 nm die. Active structures of both die have been tested and are functional.
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The 45 nm top die includes SRAM, ROM and standard cells. The 130 nm bottom die includes routing from the top die to the package. |
The top die is in a 45 nm technology and includes SRAM, ROM and standard cells. The bottom die is in a 130 nm technology and includes the voltage regulator, buffers, thermal and mechanical sensors, daisy and delay chains, as well as all the routing from the top die to the package.
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point is that they could use 130 gen for part of the circuit. Only the circuit components that required 45 nm for performance were fabed with that gen technology. This has always been claimed for 3D IC but now it is proven.
PTFLE - 8/4/2009 7:10:51 PM CDT -
Very interesting, but I didn't think bandwidth would be a limitation for applications within the cellphone.
fg - 7/14/2009 9:34:21 AM CDT
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