Sematech Crafts ZIL Solution for 16 nm
Sematech researchers said a zero interface layer (ZIL) approach has been demonstrated, and may be brought into chip manufacturing within the next few years. By eliminating the oxide interface layer between the high-k dielectric and the silicon channel, the EOT can be sharply improved, reducing short channel effects while improving the drive current.
David Lammers, News Editor -- Semiconductor International, 6/29/2009
Sematech (Austin, Texas) researchers said they are confident they can remove the oxide interface layer between the hafnium-based high-k layer and the silicon channel, sharply improving the equivalent oxide thickness (EOT) within the next two to three years. By removing the interface layer, a Sematech team was able to reduce the EOT to 0.59 nm for a hafnium-based gate stack applicable to 16 nm CMOS devices.
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Raj Jammy, vice president, Sematech |
Sematech has been developing its high-k/metal gate stack process, which involves a hafnium oxide gate dielectric, an aluminum oxide (AlOx) cap for the PMOS and a lanthanum oxide (LaOx) cap for the NMOS, followed by a TiN-based gate electrode, noted Raj Jammy, vice president of materials and emerging technologies. The approach is relatively simple, and meets the threshold voltage tuning levels required for CMOS integration.
For the 45 and 32 nm nodes, however, the oxide interface layer accounts for ~50% of the EOT. "When we look at the roadmap and how to scale past the 32 nm generation, we are focused on the interface layer," Jammy said. "That is a relatively low-k SiON layer, and eliminating it has a big return on investment. We have shown that we are able to get the interface layer out completely, and get the high-k next to the silicon, which is what we call the ‘zero interface layer' or ZIL approach. We believe that ZIL will take us down to 22 nm and beyond."
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By reducing and then eliminating the oxide interface layer, Sematech researchers cut the EOT sharply. (Source: Symposium on VLSI Technology) |
Also, the learning achieved by developing a ZIL flow for silicon channel devices would be applicable to the germanium- or III-V-based channels created for the heterogeneous devices that may be applied when silicon channels run out of steam, Jammy said. That transition may occur at the 12 nm node.
Oxygen vacancies a challenge
Paul Kirsch, director of the front end process group at Sematech, said the interface layer has been ~5 Å thick, or ~50% of the electrical thickness of the entire gate stack, which he said "dilutes the value of using a high-k/metal gate solution."
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Although the physical thickness of the high-k layer is ~2 nm, the electrical oxide thickness (EOT) is reduced to 0.59 nm. |
Sematech researchers went to the recent Symposium on VLSI Technology in Kyoto, Japan, to deliver a paper on the zero interface approach. Elimination of the interface layer presents fewer challenges than switching to a new dielectric material based on aluminum, zirconium or other metals, they argued.
Kirsch said traditional thinking has argued that the interface layer was needed to preserve high electron and hole mobilities. Although the research shows that there are additional scattering mechanisms when the SiON interface layer is removed, the impact on final performance is not as bad as expected.
The Sematech paper at the VLSI Symposium reported that electron scattering due to coupling to soft optical phonons in the high-k film does not increase "as could be expected with a thinner IL. This excludes phonon scattering as a major contributor to the observed mobility reduction," the researchers said. The paper, titled "Gate First High-k/Metal Gate Stacks With Zero SiOx Interface Achieving EOT=0.59 nm for 16 nm Application," concluded that "mobility improvement may be achieved by reducing the oxygen vacancy-related defects near the interface with the substrate making ZIL HfOx a promising candidate for 16 nm node CMOS technologies."
As the industry moves to 16-20 nm gate lengths at the 16 nm node, devices are "entering the range of ballistic transport," Kirsch said. "Mobility does degrade with a zero interface, but it is not as critical as it was in the old days, so to speak. And the drive current still improves."
The zero interface approach uses existing materials and equipment, including the precursors developed for hafnium-based dielectrics. And the Ion/Ioff improves 3-4% per angstrom of EOT scaling, he said.
"The industry needs to improve EOT scaling to improve performance and control the short channel effects," Kirsch said. Although there are challenges as the high-k dielectrics move closer to the silicon channel, he said he believes a zero interface approach will be adopted "within the next couple of years."
"To achieve the performance and power dissipation targets on the roadmap, we have to strongly consider this zero interface type of approach," he said.
Jammy said the ZIL technology will be discussed at SEMICON West July 14 at 10:30 a.m., at a TechXPOT seminar on materials and processes.
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