Thin SOI Devices Shine at VLSI Symposium
At the 2009 Symposium on VLSI Technology in Kyoto, Japan, an IBM R&D team described fully depleted CMOS devices created on extremely thin silicon-on-insulator (ETSOI) wafers, aimed at the 22 nm node and beyond. A Hitachi team presented SRAMs fabbed on ultrathin buried oxide SOI. Both avoided ion implantation steps.
David Lammers, News Editor -- Semiconductor International, 6/18/2009
IBM researchers went to the Symposium on VLSI Technology in Kyoto, Japan, to present a fully depleted CMOS process integration scheme for extremely thin silicon-on-insulator (ETSOI) devices, aimed at the 22 nm node and beyond.
The IBM process flow avoids implant steps, as does another thin buried oxide (BOX) SOI process flow presented at the symposium this week by researchers from the Hitachi Central Research Laboratory (Kokubunji, Japan). The Hitachi team said that in conventional CMOS on thin BOX substrates, halo implantation can cause damage to the gate oxide, especially at the gate edge. For the ultrathin BOX technology, which Hitachi calls Silicon on Thin BOX (SOTB), ion implantation was avoided to prevent damage to the oxide. Hitachi created SRAM devices that operated at 0.6 V, and said the ability to reduce the operating voltage was due to better control of the threshold voltage variations through the use of the thin buried oxide.
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IBM demonstrated ETSOI devices with an active silicon layer of <2 nm. |
The IBM team developed prototype devices using its high-k/metal gate technology. The source/drain (S/D) and extensions were doped by an in situ epitaxial process, resulting in an implant-free flow to successfully reduce series resistance below 200 Ω/μm. "A zero-silicon-loss process was developed to eliminate loss of the thin SOI layer during gate and spacer processes, enabling structural demonstration of sub-2 nm ETSOI," the IBM team reported.
Even without strain boosters, the IBM paper claimed a "remarkable" pFET drive current of 550 μA/μm with a 6 nm SOI channel and a 25 nm physical gate length. A 15% reduction in parasitic capacitance was achieved by a faceted raised source/drain (RSD). "Excellent electrostatics and small device dimensions render ETSOI devices suitable for the 22 nm node and beyond," the IBM team reported.
IBM's VLSI symposium presentation said fully depleted SOI with an extremely thin body has advantages, including superior control of the short channel effect with negligible dopant fluctuation. However, ETSOI poses new challenges such as extension engineering, high series resistance, increased parasitic capacitance and nearly zero tolerance of silicon loss. The performance of the pFET is of particular concern, because the strain techniques that work well for pFETs in conventional CMOS, such as embedded silicon germanium (eSiGe) stressors, are not possible with ETSOI.
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Extensions are created by an RTP anneal to drive dopants in the RSD toward the ETSOI channel. (Source: IBM) |
The IBM ETSOI process flow starts by thinning the SOI wafer by thermal oxidation and wet etch, followed by high-k/metal gate creation, defined by an optimized gate etch process, which stops on the ETSOI layer. A nitride layer is deposited and etched by a partial spacer reactive-ion-etch (RIE) step to intentionally leave a thin nitride on the ETSOI. The remaining nitride on the SOI layer is removed during the subsequent RSD epi preclean with an HF acid etch to form the offset spacer, with minimal silicon loss. An epitaxy process was developed to form a faceted RSD with in situ doping. The faceted RSD reduces source and drain resistance while minimizing gate-to-S/D parasitic capacitance. Extensions are created by an RTP anneal to drive dopants in the RSD toward the ETSOI channel, the IBM team said.
"A primary advantage of our process flow," the IBM team reported, "is that S/D and extensions are formed without implantation, therefore eliminating implant-related issues such as ion straggling, amorphization of the entire ETSOI, damaging BOX and segregating dopants into the damaged BOX."
The IBM presentation in Kyoto coincides with an announcement by Soitec (Bernin, France) that it is readying its ability to manufacture SOI wafers with a thin top layer of silicon (<20 nm), with a thickness uniformity tolerance of ±5 Å.
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