IMEC Tips 10 nm Options at Tech Forum
IMEC Fellow Marc Heyns described R&D directions at the consortium's recent technology forum, including 10 nm devices with high-mobility channels based on germanium and III-V materials.
Laura Peters, Editor in Chief -- Semiconductor International, 6/11/2009
At the IMEC Technology Forum in Brussels, Belgium, IMEC Fellow Marc Heyns presented various CMOS transistor possibilities for 15 nm and beyond. "We are at the brink of a new era of innovation," Heyns said, adding that he sees no fundamental barriers to scaling to the 10 nm node. One roadmap involves the integration of new materials and structures over time (Fig. 1).
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| A gradual transition to high-mobility materials using germanium, III-Vs and a possible move to quantum well CMOS transistors will enable <22 nm devices and scaling to 10 nm. |
As a successor to the state-of-the-art high-k/metal gate approaches today with strain engineering, high-mobility channels with germanium and III-V materials are likely to be used in next-generation transistors. Eventually, a move to alternative, 3-D FETs may occur that would be compatible with chip-stacking methods. Beyond high-mobility surface channel or quantum well Ge/III-V transistors, advanced materials including carbon nanotube (CNT) interconnects and graphene are likely to play a roll in the move to 10 nm node devices.
Heyns said that recent studies at IMEC revealed that germanium oxide (GeO2), when grown under the right conditions on silicon, is actually a better insulator than the SiO2. The stack is Ge/Si/SiO2/HfO2. "We can take advantage of the proven Si/SiO2 interface with selectively grown germanium epi underneath the silicon." The key to growing the germanium interface on silicon substrates is using selective germanium epitaxy (with a high density of Ge+4), followed by silicon epi using trisilane at 350ºC, rather than the traditional higher-temperature silane deposition.
The selectively grown germanium layer (after shallow trench isolation) is strained. The 3-monolayer silicon has three monolayers of SiO2, reducing germanium in-diffusion and controlling interface trap density. Heyns stated that the GeO2 by epi is compositionally different than GeO2 deposited by ALD. He added that a major challenge is achieving electrical passivation of the high-mobility/high-k interface.
Figure 2 shows the pMOS process flow. IMEC researchers have demonstrated 40% higher drive current than silicon devices with 1.2 nm equivalent oxide thickness (EOT) and an EOT of 0.85 nm using an ALD HfO2 thickness of 2 nm. However, for the nMOS device, the ultrathin silicon layer is so highly strained it changes the bandgap. "So silicon passivation is definitely not the way to go for nMOS devices," Heyns said.
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| The germanium pMOS device achieved 0.85 EOT using a 2 nm HfO2 gate dielectric. |
To further reduce EOT, the pMOS device could go to III-Vs, while a germanium nMOS transistor could also begin to use III-V materials (likely (In)GaAs) in a quantum well or surface channel device. The InGaAs would be grown after germanium removal. Using a molecular beam epitaxy tool, good germanium surface passivation can be achieved by in situ deposition of Al2O3 on GeO2. The researchers are investigating metal organic CVD (MOCVD) as well for selective (In)GaAs after STI for pMOS. Heyns cautioned that the way these transistors are characterized and modeled will be different than in silicon devices. He also indicated that any GaAs or (In)GaAs surface must avoid oxidation, which reduces the stress and causes Fermi level pinning. "We determined that the real defects are created not from the high-k but the III-V material beneath it," he said.
To further improve drive current and reduce leakage, a TunnelFET structure (Fig. 3) has demonstrated first-pass feasibility, according to Heyns. "Power is a big problem and with high-mobility materials there are smaller bangaps, so further Vdd scaling is possible," he explained. The approach uses etched nanowires such as InAs nanowires, which grow on patterned Si(111) 40 nm defined holes. These III-V on silicon approaches are particularly appealing for optical applications.
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| The Tunnel FET offer lower Vdd scaling due to its use of high-mobility, small bandgap materials. |
Graphene, which is a zero-bandgap semiconductor with very high carrier mobility, is showing great promise, particularly for interconnects. While the current capacity for copper is ~106 A/cm2, it is ~109 A/cm2 for carbon nanotubes.
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