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Novellus Improves Clean Process for Speed Max Gapfill Tool

Novellus said it has improved the in situ clean steps for its CVD gapfill platform, reducing particles and contaminants significantly. Dielectric films tend to adhere to the process chamber components during the deposition process, and must be removed on a periodic basis.

Staff -- Semiconductor International, 6/9/2009

Novellus Systems Inc. (San Jose) said it is able to reduce contamination significantly with an in situ chamber clean process for the company's Speed Max High Density Plasma (HDP) CVD gapfill platform.

The clean process reduces defect densities and out-of-control (OOC) particle events through improved NF3 delivery and optimization of the Speed Max platform's "bright" (coil-assisted) and "dark" (remote plasma) cleans. The advantage, said Doug Hayden, director of technology for Novellus's Gapfill Business Unit, is the ability to remove film buildup from targeted locations within the process environment.

Voids are caused by gapfill particles in 45 nm devices.
Voids are caused by gapfill particles in 45 nm devices.

Novellus said that the Speed Max clean process reduces overall mean particle adders by 3× and OOC events by 50%. In addition to "bright" and "dark" cleans, the approach involves an isothermal environment and fluorine-resistant materials to minimize particle "shedding," a key contributor to random particle events. Also, the multi-step clean approach reduces the amount of NF3 usage, reducing costs.

As transistors shrink, dielectric gapfill aspect ratios are creating defect-control challenges. Dielectric films that adhere to the process chamber components during the deposition process can be a source of particles and need to be efficiently removed on a periodic basis. The occurrence of a random killer defect event during the gapfill process can cause a failure of the dielectric isolation between transistors or memory cells, Hayden said.

Surface particles arising from chemical mechanical planarization (CMP) steps can provide another failure mechanism by increasing scratches, and contaminants or interconnect metal deposited during subsequent process steps can fill in these voids or scratches, causing a high-current leakage path between the cells that causes yield loss and device failures.

Gapfill defect densities improved with the in situ clean process for three different customers at different technology nodes. (Source: Novellus Systems Inc.)
Gapfill defect densities improved with the in situ clean process for three different customers at different technology nodes. (Source: Novellus Systems Inc.)

 

Achieving single-digit particle performance with particle sizes <90 nm in diameter will enable device manufacturers to enhance their 45 nm yields, Hayden said, and "will be a necessity to yield 32 nm devices."

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