Emerging Trends in Advanced Packaging
As electronic products find applications in personal, healthcare, home, automotive, environmental and security systems and become ubiquitous in everyday life, new packaging technologies and materials will be required.
Mahadevan Iyer, Texas Instruments, Dallas -- Semiconductor International, 6/1/2009
Electronic products continue to find new applications in personal, healthcare, home, automotive, environmental and security systems. Advancements in packaging co-design, low-cost materials and reliable interconnect technologies are critical in enabling the innovative packaging solutions required to help drive the industry forward (Fig. 1).
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| 1. Packaging technology trends reflect applications and end equipment. |
Among the many packaging challenges that must be addressed is the continued development of powerful co-design tools to shorten development cycles, and enhance performance and reliability. Continued pitch reductions and the use of 3-D package interconnects in single-chip and multichip components, and IC integration with sensors, energy harvesting and biomedical devices require packaging materials that are low cost and can be easily processed. Several challenges need to be addressed to support wafer-level bumping and lower-cost wafer chip-scale packages (WCSPs) focused on sub-60 μm pitch bumping. And finally, we must be prepared to address unique packaging challenges of high-growth MEMS devices in automotive, portable handsets, consumer and medical electronics.
Package design and modeling
Modeling design tools have long been used in the development of electronic systems, including electrical and thermal models to predict fundamental performance capabilities to ensure suitability to the given task. Thermomechanical modeling is used to validate manufacturability and reliability targets. The goal of the analysis is to create a design that works at the specified performance on the first iteration. As the complexities of electronic systems grow, and as design cycle times shorten, more attention is focused on transforming modeling into a co-design tool used at the outset of design projects to optimize chip layout, architecture and partitioning for maximum performance at the lowest cost.
Today's commercial modeling tools have limitations that must be addressed to enable full co-design. Current tools take inputs from CAD databases and usually require some degree of laborious manipulation to form the mesh used to calculate physical characteristics. Different tools use proprietary approaches to meshing, which then require separate remeshing for each tool. Repetitive meshing wastes valuable design time, increasing modeling costs. Remeshing also limits the feasibility of performing multiple trade-off analyses between the three disciplines.
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| 2. Complex die stacking and interconnect schemes require careful mechanical and electrical modeling. |
Future tools must interactively analyze all three disciplines by accessing the same CAD database, perform meshing without user intervention, and optimize the design through cost-function minimization of the appropriate parameters. Software tool vendors must address these critical needs or risk becoming irrelevant (Fig. 2).
The goal of electrical modeling is to accurately analyze the entire system from source chip and package through the PCB and into the receiving chip. Increasing system performance and architecture complexities challenge electrical modeling. At higher frequencies, more structures throughout the system approach significant fractions of a wavelength with concomitant risks of coupling through electromagnetic interference (EMI). Use of transmission lines or waveguides is increasing, making timing analysis more critical and requiring that manufacturing variations such as dielectric thickness and trace widths be included. For 3-D packaging approaches such as stacked die, stacked packages and interconnect technologies such as through-silicon vias (TSVs), engineers must consider coupling to the above-die and below-die structures. To handle these new complexities, the industry needs new solution algorithms and problem partitioning to overcome current constraints on solution speeds and problem size.
Engineers use thermal modeling to optimize the power handling capacity of die, packages and systems to ensure junction temperature limits are not exceeded. A thermal level problem is a system (and even a building) issue because the system and building are responsible for heat sinking the individual chips. Airflow, system enclosure, external environment, neighboring component locations and other factors must be included to accurately predict system operating temperatures. 3-D packaging, with its concentration of power into ever-smaller volumes, requires adequate measures be taken to manage the increased power density down to the resolution of die hot spots. Thermal modeling is being challenged to address this level of system complexity, and industry collaboration is underway to develop appropriate compact models and boundary conditions for different scale domains.
Thermomechanical analysis focuses on ensuring optimal manufacturability and reliability of electronic components, and is guiding reliability research of new TSV technologies and materials selection for on-die dielectrics. System design is being influenced to improve reliability under impact loading and vibration. MEMS are being co-designed to tune device performance to operate in symphony with the inevitable package stresses. Upfront, the engineer must know accurate materials properties such as thermal expansion, modulus, tensile strength, adhesion behavior and fatigue behavior to provide valid reliability predictions. Adhesion and fatigue must be obtained at room temperature as well as at solder reflow temperature and temperature cycle extremes.
Interconnects
Traditional interconnect choices include wire bond and solder flip-chip for cost-sensitive and high-performance applications, respectively. As the electronics industry has become more consumer-product-oriented, cost has become more important even for high-performance products. The required portability of consumer products has also increased the importance of size, driving reduced pitch for both wire bonds and solder flip-chip interconnects and fueling development of new interconnect technology.
Somewhere below ~150 μm pitch, traditional solder bump flip-chip interconnect no longer provides adequate manufacturability or reliability for any but the smallest die. Die-to-substrate standoff is at or below half the bump pitch, impacting manufacturability and reliability of flip-chip devices. Below some threshold, resistance to underfill flow from the very small channels formed by adjacent bumps and the die and substrate surface overcomes capillary action.
Copper pillars with solder caps are increasingly being used to replace traditional solder bumps, and can offer a flip-chip solution at wire-bond pitches. Unlike solder interconnects, copper pillar-based interconnects can have a height/diameter aspect ratio of >1:1. For a given die pitch, the pillar-to-pillar and die-to-substrate spacing are larger than for solder interconnects, leading to improved underfill manufacturability and reliability. The tradeoff for increased standoff is reduced die-to-substrate coplanarity tolerance, as less starting solder height allows less joint height variation.
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| 3. This copper column shows a 2.5:1 aspect ratio. |
Copper column interconnect technology is being developed at the university level. Potential benefits include high structural integrity due to the all-copper construction (no solder or intermetallic compounds), sub-25 μm pitch, and no underfill requirements due to the high aspect ratio (≥4:1) and strength of the interconnect. Copper columns are plated from the die and/or substrate, and the joining process uses electroless copper plating to fill the gap between the copper columns or copper column and pad (Fig. 3). This allows for a relatively large die/substrate coplanarity tolerance.
Materials
New materials drive different process interactions and change the physics of interconnects, interfaces and reliability. For example, a change to copper wire in bonding introduces new phenomena that must be studied and characterized.
Leadframe package manufacturability, cost and reliability are strongly affected by the introduction of green materials. Other factors include high-temperature ambient such as in automotive engine compartments, high-voltage (500–1000 V) requirements, high-conductivity die-attach materials for high-power ICs, and thick conductors for high-current carrying capacity. Replacements for traditional materials for leadframes, mold compound and interconnect wires are emerging, including aluminum leadframes, gold-wire-free interconnect and low-cost, injection molding used with ultrathin silicon chips.
Underfill is another critical material for most flip-chip packages. Today's underfill materials must meet several competing requirements. They must behave well during the underfill process step, flow quickly through ever-shrinking openings, protect the solder joints and active circuitry from thermomechanical stress, and maintain performance after repeated exposure to high temperatures and moisture. The newest underfills incorporate submicron fillers with tight size distribution, and multiple additives to tailor adhesion, modulus, coefficient of thermal expansion (CTE) and glass transition temperature (Tg) to successfully reinforce new, stiffer lead-free solders while maintaining low stress on the ultralow-k dielectric active circuitry stack.
In choosing underfill materials, engineers must consider the combination with the solder flux used in the chip-attach reflow process. Fluxes for lead-free solders are more active than for tin-lead solder, which leads to more aggressive post-reflow flux residue. These residues can react with underfill material, creating a mixture with non-optimal properties. One potential solution is to use a cleanable flux and remove the residue before applying the underfill material. This approach requires additional equipment and process steps. If a no-clean flux is used, some residue will be present and the behavior of the underfill material in the presence of flux residue must be characterized (Fig. 4).
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| 4. Post-temperature cycle cross-sections of a non-optimized (top) and optimized (bottom) flux-underfill combination. |
Fine-pitch bumping
Portions of the gaming and wireless spaces use — or are considering — flip-chip packages with bumps at sub-60 μm pitch vs. standard pitches of 150 μm. Potential solutions to grow adoption are to reduce the bump size or move to a thicker stud covered with a tip of solder to provide standoff between the die and substrate. Tighter-pitch bumps and potentially increasing the thickness of plated copper brings challenges and opportunities for materials and processes in this space.
For bumps formed through electroplating, the challenges start with the selection of photoresist material. Captive plating, in comparison to mushroom plating, is a requirement for bumps in this pitch range that corresponds to thicker resists and aspect ratios that may exceed 3:1. Positive and negative resists are available that provide the required thickness. Positive resists have advantages in slope and strip ability, while negative resists have advantages on exposure energy and develop times. To date, resist film selections have at this point demonstrated aspect ratios to 4:1, with greater capability expected. Certain materials demonstrate greater capability or challenges for chemistry wetting into high-aspect-ratio structures.
High-aspect-ratio resist openings create wetting challenges for plating chemistry. Plus, the increase in copper thickness requires an increased plating rate to maintain throughput. However, as uniformity of plated structures tends to correlate to plating rate, further development in plating technology is needed to produce satisfactory results.
Small structures also impact tool and chemistry selection. When processing bumps with pitches of 150 μm and larger, the bump structures provide a wide process window for toolsets and chemistries. Batch toolsets and aggressive etch chemistries producing large undercuts of the bump structure become a detriment to quality as the structures move from a CD of 80 μm to 30 μm and below. These challenges are solved by moving to single-wafer process tools and less aggressive etch chemistries.
Tighter bump pitches reaching >60 μm have become a reality with the correct selection of materials, toolsets and processes to create a robust high-volume process. For plating processes, these cover areas of photolithography tool sets and materials, plating chemistry wettability and plating rate, and strip and etch tool sets and processes.
WCSP
Wafer-level chip-scale packaging (WCSP) application spaces are expanding into new areas and are segmenting based on pin count and device type. The foundation of passives, discretes, RF and memory devices is expanding to logic ICs and MEMS. As die size and pin count increase, board-level reliability becomes a greater challenge.
The low-pin-count WCSP segment has matured over the past decade, with numerous sources delivering high-volume applications across multiple wafer diameters and expanding into various end-market product spaces. With infrastructure and high volumes in place, a major focus area is cost reduction, especially on low-pin-count devices, but also in higher-pin-count devices including 300 mm wafers.
Higher-pin-count devices have created new challenges. In cases where fan-in techniques are insufficient because of silicon area, fan-out technologies have been introduced. These techniques have manufacturing and cost challenges, with one example being die placement accuracy on a large carrier. The fan-out techniques also have potential for system-in-package (SiP) applications, and could be an interim step or compete with alternative solutions such as stacked packaging options using TSVs.
Cost savings are expected from simplifying the current construction. Another source of savings is working with material suppliers to develop next-generation materials.
Special considerations for MEMS
SiP technology has begun to integrate MEMS devices, along with other logic and application-specific circuits. MEMS applications cover the domain of inertial/physical, RF, optical and biomedical, and these applications demand different types of packages such as open cavity packages, over-molded packages, wafer-scale packages and special types of hermetic packages. These microsystems must have the ability to operate in humid, saline, high-temperature, toxic and other harsh environments (Fig. 5).
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| 5. Fan-out techniques, using redistribution layers or alternatives, may compete with stacked packaging with TSVs. |
3-D packaging technologies with TSVs provide a solution to stack a MEMS device with other chips. TSVs combined with wafer-level packaging enable smaller form factors. Potential applications include optical, microfluidics and electrical switches.
Medical, security, automotive and environmental applications are among the exciting areas emerging in electronics today with high growth potential. Most of these applications will require sensors, or MEMS and ICs as part of the system. Stand-alone systems will operate with very little power from batteries or energy-scavenging techniques. Wide use of such devices in personal healthcare will be incumbent upon their value, ease of use and price.
There are several MEMS opportunities in medical devices such as in-vitro diagnostics, lab-on-a-chip and drug delivery. MEMS-based microfluidics will be a critical technology to support these applications. Other opportunities include three-axis accelerometers, pressure sensors, energy scavengers and silicon microphones for hearing devices. Implantable devices also require unique packaging to support reliable performance in the harsh environment inside our bodies.
Reducing packaging cost is the major challenge facing MEMS devices, and it is driving more standardization and package commonality in form factors. Other critical challenges include stress management (especially for pressure and inertial sensors), particle avoidance, positional assembly tolerance, pressure control and hermeticity.
Conclusion
Advanced packaging plays a crucial role in driving products with increased performance, low power, lower cost and smaller form factor. There are challenges associated with chip/package co-design and in the application of cost effective materials and processes for various reliability requirements. The industry requires innovations in technology and manufacturing to meet current demands and the ability to operate equipment in high volume with large throughput. Innovative packaging solutions are needed for energy efficiency, healthcare, public safety and more.
| Acknowledgement | ||
| The author would like to thank the following people at TI's Semiconductor Packaging for contributing to this article: Darvin Edwards, manager, design and modeling; Patrick Thompson, manager, ceramic flip-chip BGA; Masood Murtuza, manager, materials/processes and characterization; David Stepniak, manager, wafer chip-scale packaging; and Mario A. Bolanos, manager, strategic research and collaborations. | ||
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