Downturn to Spur Shift to 3-D Packaging
The past several semiconductor downturns have resulted in transitions from one generation of packaging to the next. This one's no exception. "Out of this downturn, we're rapidly shifting from 2-D to 3-D packaging," said Jim Walker, vice president of semiconductor manufacturing research at Gartner Inc.
Sally Cole Johnson, Contributing Editor -- Semiconductor International, 5/27/2009
What impact is the global economic downturn having on the advanced packaging industry? Some ramifications are obvious, while others are much more subtle.
Jim Walker, vice president of semiconductor manufacturing research at Gartner Inc. (Stamford, Conn.), said during every one of the major downturns (1985, 2001 and 2008), the semiconductor packaging industry has moved from one generation of technology to the next. The downturn in 1985 spurred the shift from through-hole technology to surface mount. Companies went from dual inline packages (DIP) to small outline (SO) and plastic leaded chip carrier (PLCC) and quad flat pack (QFP). And after the 2001 Internet bust, the industry moved from leaded packages to leadless leadframes and from peripheral packages to array packages, as mainstream ball grid arrays (BGAs) and chip-scale packages (CSPs) really took off.
“This time we’re transitioning from 2-D to 3-D,” Walker said. “We’re stacking packages, wafers, die, and even seeing through-silicon vias (TSVs) start to take off as well. Even though package and die stacking have been around for a few years now, as we come out of this downturn we’re going to go from 2-D to 3-D in a big way with the various assortment of options from a manufacturing standpoint — whether it’s package-on-package or stacked die or TSVs. Some people might disagree about the timing of these transitions, but each time we’ve come out of a big recession in the semiconductor industry it was because newer technology adoption led the way.”
Copper, flip-chips, TSVs take off
The shift from gold to copper wire bonding is starting to really pick up. “The prices of gold are still high and this makes copper a lower-cost alternative,” Walker said. “Even flip-chip becomes more cost-competitive — as long as you’re using lead-free bumps and not gold bumps.”
There is also increasing interest in flip-chips, Walker reported, mostly because the industry needs to go to that wafer-level type of interconnect for performance reasons. “Right now there’s really no other fast, short interconnect option,” he said.
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| Industry downturns accelerated the adoption of next-generation packaging technology. (Source: Gartner) |
Interest in TSVs as an interconnect is also making headway. “I don’t see any ‘gotchas’ with TSVs — no technology limitations, except for maybe design criteria and software for 3-D. There aren’t many problems from a technology, manufacturing or equipment standpoint,” Walker said. “It’s a matter of adopting the designs to go to TSVs and then making the infrastructure available. If you look at TSV infrastructure — manufacturers like EV Group (St. Florian, Austria), SUSS MicroTec (Garching, Germany) and Semitool (Kalispell, Mont.) — they increased some of their TSV-related equipment sales last year while so many other companies were going down. TSV technology is still being researched, but it’s also starting to be adopted for production.”
Many companies are switching to QFN and DFN leadless leadframe from SO packages. “This is definitely a cost consideration in going to smaller packages for the next-gen cell phones and handhelds,” Walker said.
The upside of downturns
Demand for more advanced packages is starting to come back. Many companies in the industry saw package production utilization rates plummet from ~70% to &30% in a period of just two months, during November and December 2008. “The spigot was turned off,” Walker said, adding, “At this point, January appears to have been the bottom in terms of revenue and utilization rates for the packaging, manufacturing and foundry guys. Now we’re seeing steady month-over-month increases.”
Advanced Semiconductor Engineering (ASE, Kaohsiung, Taiwan) and Siliconware Precision Industries Co. Ltd. (SPIL, Taichung, Taiwan) are forecasting decent growth rates for the second quarter, he said. “Things are starting to look a little better — we expect Q2 to be up 20-25% for packaging.”
Packaging companies tend to be a leading indicator of where the industry is headed because their inventory is stored in die banks — where wafers sit out of a fab for a month or two, ready to be used. When orders from IDMs roll in, the wafers are taken out of the die banks and put through production in less than a week, Walker explained. “When the wafers start coming off the shelves, the inventory is being depleted, production starts picking up and we start seeing units go through the factory again.”
Since the cycle time is only a week, packaging companies start seeing changes in as little as three or four weeks. “This is a trend you can see with packaging that you don’t see with the foundries or IDMs from an internal manufacturing standpoint. The SATS guys are the leading indicator of when things are starting to pick up.”
