Flip-Chip Packaging Becomes Competitive
The cost and performance benefits of flip-chip packaging, combined with the increased cost of gold bonding wire, have made flip-chip technology competitive for applications ranging from cell phones to gaming chips.
Sally Cole Johnson, Contributing Editor -- Semiconductor International, 5/1/2009
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| Flip-chip packaging has gained in popularity due to its form factor, ability to meet RF and high-performance requirements, and its cost competitiveness relative to wire bonding. (Source: Amkor) |
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Looking back 15 years ago, nearly everything was wire bonded. Today, flip-chip packaging is taking over. The basic flip-chip concept is to take a chip, place conductive bumps on the connection points, flip it over, put it face down and directly attach it to the circuit. Flip-chips eliminate excess packaging, while providing highly desirable benefits such as miniaturization, high-frequency operation, low parasitics and a high I/O density (Fig. 1).
Flip-chips can be found in nearly every hot consumer gadget from cell phones and pagers to MP3 players and digital cameras. In the server space, virtually all logic modules are flip-chip packaged. And most ASICs, gaming, graphics processors, chipsets, field-programmable gate arrays (FPGAs) and digital signal processors (DSPs) are now also flip-chip modules (Fig. 2).
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| 1. Demand for flip-chips, such as this flip-chip BGA system-in-package (SiP), is on the rise, thanks in part to rising gold bonding wire costs. (Source: STATS ChipPAC) |
The cost of gold bonding wire has been on the rise the past few years — making flip-chip even more appealing. "If we look at the cost two to three years ago, flip-chip was inherently more expensive," said Raj Pendse, vice president of flip-chip and emerging products at STATS ChipPAC (Singapore). "Flip-chip substrates typically cost two to three times the amount of a wire bond substrate, but the rising gold costs have evened out the differential in package costs. The flip-chip is becoming more cost-effective over a broader range of applications. In the past, it was used in the 1000 pin count range. It's becoming cost-effective in the 200–700 pin count range."
History of flip-chip
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| 2. This flip-chip BGA is designed for a game CPU. (Source: Amkor) |
The first application of flip-chip technology occurred in 1964, for hybrid solid logic technology (SLT) in the IBM S/360 mainframe computer, according to Peter Brofman, distinguished engineer, IBM packaging technology strategy. This consisted of a handful of bumps at a coarse pitch that incorporated a copper ball as an extra standoff to prevent shorting to passives. "True flip-chip use began in 1969 with the advent of ICs, but only peripheral-array was available," he explained. "Full area-array with metallized ceramic (MC) technology occurred in the mid-1970s. By the early '80s, IBM had an 11×11 array, on a 250 μm pitch, with Pb-5Sn solder."
In the late '80s and early '90s, Motorola, an IBM flip-chip licensee, started looking at alternatives to flip-chip ceramic carriers, leveraging new work on chip-to-carrier underfills to begin assessment of lower-cost FR4 organic materials. This work was in parallel to the advancement of buildup layers on cards, noted Patrick O'Leary, IBM packaging engineering manager, pioneered by IBM as its surface laminar circuitry (SLC) process in 1990, and largely available from multiple chip carrier suppliers by the mid-90s.
"By 1998, large microprocessor offerings were using underfills and moving to organic flip-chip buildup carriers, with 35 mm 2-2-2 carriers approaching $3 in the 2000–2001 timeframe," O'Leary said. "This flip-chip 'price of entry' was still more costly than wire bond, but the cost/performance benefit was sufficient for graphics and then gaming processors to benefit from the flip-chip industry infrastructure and complete the migration to organic flip-chip modules by the mid-2000s."
IBM has moved all of its new flip-chip single-chip modules (SCMs) to laminate carriers. O'Leary pointed out that the significant migration of processors to flip-chip drove flip-chip module compound annual growth rates (CAGRs) above 35% earlier in the decade. "Now the CAGRs are lower but still robust, as factors such as the cost of gold wires lowered the cross-over point to flip-chip to within the range of 200–700 I/O. At these lower I/O counts, there are integrated device manufacturers that will begin to eliminate wire bond from their package menus — potentially starting at the 32 nm node."
Other recent milestones in flip-chip technology include the evolution of flip-chip "bumping," or solder deposition options. Larger wafers, most notably 300 mm, drove IBM and others to migrate from vacuum chamber evaporation processes to electroplating in the mid-90s. Recently, IBM and SUSS MicroTec (Munich, Germany) worked to develop and commercialize IBM's next-generation lead-free semiconductor packaging technology, controlled collapse chip connection new process (C4NP), which is now in volume production. C4NP enables the creation of pre-patterned solder balls to be done in the front end, reducing cycle time, O'Leary explained. The solder bumps can be inspected in advance and deposited onto the wafer with one step, using technology similar to wafer-level bonding. It combines the simplicity of solder paste (stencil/screen) with the fine-pitch capability of electroplating. "Both C4NP and electroplating have 150 μm C4 pitches in production to help keep pace with the scaling of silicon features," O'Leary said.
Though IBM developed flip-chip technology to meet the needs of the mainframe computer market, it is playing an important role well beyond computers, said Frederick Hamilton, senior director of flip-chip at Amkor (Chandler, Ariz.). "Flip-chip has now expanded to use in computing, wireless, networking, telecom/datacom, automotive and consumer (HDTV) markets," he said. "But PCs remain the largest single consumer of semiconductors and flip-chip devices."
Interestingly, the average field life of a flip-chip is about 15 years — although some are now being designed for a five-year field life. "Given the basic structure of flip-chip, it can comfortably meet a 15-year field life," Pendse noted.
Key technical benefits
The primary benefits of flip-chip involve miniaturization and size savings, as well as shorter path lengths with low inductance, high I/O density, rework capability and self-alignment. Flip-chip is also considered a superior configuration for thermal management.
The flip-chip enables an area array interconnect, which means a higher I/O density and a more efficient power supply on the chip than is possible with a peripheral array. "You can feed the power to the center of the chip where it's needed. This provides a big advantage. The low parasitics associated with flip-chip are very important in RF and other applications," Pendse said. "Another advantage is that you don't have the fan-out since the connection is directly between the chip and the substrate — unlike wire bonding, which involves fan-out of the I/O from the chip to the substrate. This means you can make a much smaller package."
Technology challenges remain
As the industry moves down the technology nodes, several challenges remain. These include the need for improved package electrical/thermal performance, the constant need for miniaturization, finer bump pitch, and a shorter time to market, all at an ever decreasing cost need from the end user, according to Hamilton.
"The industry still needs to overcome issues such as air gaps within materials, bumping-type methods associated with low-k reliability, low-k reliability linked to package warpage, warpage in thin and no-core laminates," Hamilton said.
When the industry made the shift from ceramic to organic substrates, serious reliability issues surfaced. "IBM claimed a track record of zero field failures during their first 35 years of using flip-chip with ceramic substrates and high-lead bumps," Pendse noted. With organic, however, reliability issues were caused by a CTE mismatch between the substrates and die, as well as an inherent variability in organic substrates, leading to a greater incidence of field failures. "The new bond structure, new substrates and associated variability in quality, and higher CTE mismatch has created challenges we're still struggling with," Pendse added.
Another challenge is that adopting flip-chip requires a higher substrate density, so it tends to be a more expensive solution than incumbent wire-bond technology. Helped partly by increasing gold wire costs and partly by innovations in interconnect structure and substrate design, that factor is slowly being alleviated over time, according to Pendse. But it will continue to be a challenge because as flip-chip becomes more prevalent in more products, including consumer products, the cost becomes a competitive advantage.
There are other significant challenges with the selection of new and improved silicon dielectric materials that make the silicon more fragile, at the same time that the industry is looking at ultrahigh-density flip-chip arrays, according to Brofman and O'Leary. Chip-package interaction (CPI) — limited reliability, higher bandwidth and greater densities — are compelling reasons for public/private partnerships for collaboration on shared problems, they said. This is why in 2008 the state of New York announced the establishment of a packaging R&D center to tackle key flip-chip related reliability challenges. One example is electromigration, the gradual displacement of the metal atoms of a conductor as a result of the current flowing through that conductor, which is expected to become a larger concern with finer C4 pitches.
Recent trends
The next logical evolution of the flip-chip concept is 3-D integration of chips on interposers or stacked chips, according to Brofman and O'Leary. Chip and wafer thinning with through-silicon vias (TSVs) and new Cu/Cu and copper column/pillar interconnects at ultrafine pitches (50 μm) are now in development, they point out. In addition to the need to address the ongoing increases in power densities for advanced microprocessors, they believe the advent of stacked chips is creating an unusually challenging thermal management roadmap.
Packaging continues to push the envelope of materials science and technology, Brofman said. Although he views carbon nanotube (CNT) interconnects as still years away, the use of nanomaterials as a filler for underfills, thermal materials and laminate composites is likely in the near future.
There are also new trends in the deposition of materials, Brofman pointed out. "In addition to C4NP, there appears to be interest in the use of a traditional BGA attach method known as 'ball drop' for the formation of the flip-chip interconnect."
How about lead-free trends? To date, flip-chip modules have been exempted from the lead-free restrictions of the European Union's Restriction of Hazardous Substances (RoHS) directive, which could be extended to 2014. "The general consensus is that if you make the bump out of lead-free materials, there are tremendous reliability challenges," Pendse said. "Even more so when the silicon goes to 40 nm and finer nodes, because the silicon itself becomes more fragile and changing the bump to a harder structure compounds that problem." The industry is working on a different bump material and solutions to make the interconnect more compliant, he said.
This "greening" of worldwide electronics has led to a long-term trend for the movement to lead-free chip interconnects, and more users of flip-chip modules will be making the migration to lead-free modules, driven not necessarily by the implementation of new legislation, but rather the market uncertainties of not knowing if a leaded module could have barriers to certain markets in the future, O'Leary said. "Multichip modules, particularly two-chip modules, are much more popular today than just three years ago. Thinner cores (0.4 mm or less) and/or coreless organic flip-chip laminates will be investigated as options for shorter path lengths for incremental electrical performance improvements," he said. "Finally, in addition to the cost/performance improvements for 3-D integration, there are clearly compelling reasons to investigate wafer-scale processing techniques such as wafer-level chip-scale packaging."
Pendse predicts another evolution of flip-chip during the next two years into areas it hasn't penetrated much yet — such as consumer applications like audio/video, camcorders, cameras, MP3 players, digital TV, etc., which stand to benefit from RF performance and miniaturization.
Users are also pursuing low-cost flip-chip substrates. "The industry is continuously evaluating new ways to efficiently route and design interconnection of the chip to the substrate," Hamilton said. "One method being investigated is laser ablation of the signal pattern into a dielectric, followed by metallization."
In terms of thin-core substrates, as the industry migrates down the technology node path to 45 nm and below, transistors per die increases, switching speed is increasing, switching voltage is decreasing, and shorter transition paths are required with reduced parasitics, Hamilton said. "To meet this need, we've already seen the migration of the industry-standard high-performance flip-chip core thickness of 800 μm moving to 600 μm or 400 μm. As we thin the core, we bring the risk of increased substrate and package warpage, and coplanarity values that challenge today's industry-acceptable package requirements. The need for thinner core and no-core has already arrived, and the packaging process, substrate supplier and assembly material manufacturers are all working together to overcome this risk and challenge."
No-core or coreless substrates can further improve the electrical performance of the flip-chip package. Coreless substrates enable any layer to be power or ground, and provide the ability to route all inputs in one layer and have all outputs on another layer. These substrates also enable greater flexibility for the package designer.
Another trend is a molded, large-body high-performance flip-chip with exposed die top. "The advent of a molded flip-chip solution is to support both thin-core and no-core solutions that will enable the packaging to meet and exceed industry requirements in coplanarity," Hamilton said. This molded packaging solution provides increased thermal performance, allowing direct contact from die to the external heat spreader through a single layer of thermal interface material. It also enables a lower-cost solution to existing high-performance single and two-piece lidded solutions, as well as improved BGA solder joint reliability.
Last but not least, the copper pillar is yet another trend worth discussing. "Device miniaturization using a solder-bumped flip-chip packaging solution increases the risk of serious electromigration problems caused by the close proximity of adjacent bumps," Hamilton explained. "As such, the copper pillar bump reduces this risk as it enables much finer pitch between the copper pillars than are possible today with solder bumps." Other benefits include smaller die/substrate gap through pitch and alpha particle reduction compared with solder bumping.
Continued evolution, eventual replacement?
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| 3. TSVs might eventually replace flip-chips. (Source: IBM) |
How will flip-chip technology evolve from this point? Pendse said he expects interconnect technologies of the future to be very different. "Initially, it will leverage flip-chip using TSVs interconnected using microbumps, which is different but in the same league as flip-chip," he said. "Moving forward, there may be better techniques to bond chips together. Then, TSVs themselves may be viewed as a form of interconnect. Flip-chip may eventually be phased out in favor of other approaches." One approach is the TSV as an interconnect (Fig. 3), and another is fan-out wafer-level packaging (FOWLP), also known as "chips-first packaging."
Hamilton also pointed to flip-chip use as a key interconnect technology for next-generation 3-D IC architectures. "Interconnect and package technologies have very long lives," he said. "There are large numbers of DIPs (through-hole interconnect) used today, even though flip-chip applications and technologies are expanding rapidly."
Brofman said there is potential for copper/copper bonding or copper studs/pillars, particularly in 3-D integration, to replace the traditional deposition flip-chip solder material sets. "Small form factor, low I/O, chip-first packaging techniques are also now in development with certain IDMs, and are showing early promise to replace or supplement the use of low-end flip-chip modules," he said.
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