Infrastructure Still Inhibits 3-D ICs
The industry is challenged to identify the most cost-effective stacking, bonding and integration methods.
Ruth DeJule, Contributing Editor -- Semiconductor International, 5/1/2009
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| 1. The EVG aligner shown in this Class 100 cleanroom facility in Singapore aligns pairs of wafers containing millions of high-density TSV interconnects. (Source: Tezzaron) |
Over the past two decades, the concept of 3-D integration has intrigued the semiconductor industry (Fig. 1). With associated concerns regarding costs and infrastructure, "it has taken time to get comfortable," said Robert Patti, CTO at Tezzaron (Naperville, Ill.). However, as the challenges of continued device scaling mount with each new generation, more resources have been dedicated to making 3-D technologies feasible and cost-effective.
The area that stands to benefit the most from 3-D integration is the low-margin, high-capital memory sector. For these cost-driven fabs, to get more bits for the dollar, "they need to have eight-layer DRAMs in the next 12–18 months," Patti said. Halving the cost per bit requires simultaneous advances in processing and device design.
This article describes the status in 3-D technologies, what is needed to achieve 3-D devices that fully realize the potential benefits offered, and what obstacles may be slowing down the commercialization process.
3-D IC technologies
Die stacking and wafer bonding are fundamental to 3-D IC processing. Through-silicon vias (TSVs) make stacking effective and wafer thinning is a necessary enabler, allowing for short TSVs and manageable stack sizes. Special wafer handling is necessary only if wafers are thinned before bonding, but that is not always the case.
Still a new technology in terms of manufacturability, each 3-D IC step brings into question the most efficient and cost-effective methods: Stack wafer-to-wafer (W2W) or die-to-wafer (D2W)? Bond with metal, adhesives or direct oxide? Create TSV and thin wafers before or after bonding? In the flow of advanced technology integration, there is a blurring of lines among wafer, packaging and board technologies (Fig. 2).
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| 2. The blurring of lines among wafer, packaging and board technologies is shown in the flow of advanced technology integration. (Source: IMEC) |
Possibly the best understood steps are the TSV fabrication processes — etching, liner deposition, barrier deposition and metal fill — with multiple equipment vendors offering solutions. Steps such as bonding the wafers to carriers or thinning the wafers on the carriers are more challenging, and only a few companies currently offer such solutions.
Availability
Fully functioning 3-D prototypes existed five years ago, and the first commercially available 3-D products were CMOS image sensors with TSVs formed from the backside to contact pads on the sensor. Patti said that by year's end, double-stack 72 Mb devices, designed for direct attachment to a microprocessor, will be available (Fig. 3), and he expects other 3-D memory chips with up to five memory layers using TSVs soon thereafter.
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| 3. This schematic illustrates two memory devices stacked together and integrated with a microprocessor to form five layers acting as a single 3-D IC. (Source: Tezzaron) |
To date, no devices incorporate all three 3-D integration technologies — TSVs, thinning and stacking/bonding. Yet to maintain and increase performance in high-speed memory at DDR3 and above, 3-D stacking along with TSV and 3-D specific device designs will be necessary.
Beyond processing steps, a "true" 3-D IC implies different things to different players. A 3-D IC in the truest sense comprises multiple layers of circuitry, TSVs and layers acting together as a single device.
Wafer/device stacking
A variety of options have been proposed for the actual stacking of die, and packaging of the stacks. The industry is debating between wafer-to-wafer and die-to-wafer stacking, with the process requirements of high assembly yield, and low complexity and cost. The choice will be determined based on application and economic grounds.
The industry is currently focused on two bonding methods: metal-to-metal, which uses the preferred foundry-based TSV technology and has the advantage of simultaneously forming the mechanical and electrical bonds, and oxide bonding. EV Group (EVG, St. Florian, Austria) has been quick to point out that current copper-copper thermocompression bonding is very slow (~8 bonds/hr in a four-chamber tool) as opposed to oxide bonding, which requires via-last processing but is capable of performing 25 bonds/hr in a single-chamber tool.
Copper bonding is a two-step process with an initial step of aligning two wafers to each other using a face-to-face alignment technique, such as "mask field" technology. Next the wafers are annealed at 400°C with a high contact force in the range of 20–100 kN. During the seven-minute anneal, surfaces interdiffuse with essentially no loss of conductivity, relative to conventional metallization, said Paul Lindner, executive technology director at EVG. The bond interface does not add a measurable resistance to the interconnect.
With a high alignment accuracy of better than 1 μm, which is expected to be in the sub-0.5 μm range within the next two years, interconnect pitches of 6–10 μm can enable high interconnect densities of ~1–3 million interconnects/cm2. For the next 2–3 years, alignment capability will not be the bottleneck.
Oxide diffusion bonding is 3× faster than copper bonding. However, the electrical interconnect is formed after the bonding, thus requiring an extra process step and potentially a level of complexity. Still, from a throughput point of view, it is more attractive than copper diffusion bond processing. "The challenge is not feasibility nor equipment technology anymore," Lindner said. "It's an issue of entering into volume manufacturing with leading products at an attractive cost level."
New stacking solutions
What is needed is a stacking solution with the speed of oxide bonding, which uses foundry-based vias to form metal-to-metal bonds upon bonding, noted Phil Garrou, 3-D consultant from Microelectronic Consultants of North Carolina (Research Triangle Park, N.C.).
One such technology is Ziptronix's (Morrisville, N.C.) Direct Bond Interconnect (DBI) covalent bonding technology, which enables room-temperature W2W or D2W bonding. With DBI, nickel can be used to interconnect to copper, tungsten or aluminum TSVs, while providing for adequate planarity of the oxide/metal interface to achieve a strong, reliable bond.
A different oxide bonding technology available from Soitec (Grenoble, France), Smart Stacking, allows W2W stacking of partially and fully processed wafers, including metal interconnects. Smart Stacking is a low-temperature (&400°C) molecular wafer bonding technique that minimizes process-induced damage, distortion and stress, said Bernard Aspar, vice president of the Tracit business unit, within the Soitec Group (Bernin, France).
Surface preparation consisting of standard chemical mechanical planarization (CMP) and cleaning chemistries produce high bonding energies (in the range of 1 J/m2) and good yield, Aspar noted. A high degree of alignment accuracy (better than ±1 μm) can be achieved, allowing stacking of fully processed wafers. In addition to crystalline silicon, this method can be used to bond fused silica, glass and polysilicon carbide.
Already fully isolated from a handle wafer, silicon-on-insulator (SOI) wafers can be readily transferred onto another processed wafer. For unique 3-D structures, SOI substrates can also be built with embedded cavities for thermal cooling or multiple layers can be stacked.
Soitec recently partnered with Léti to develop a low-temperature non-thermocompression copper-to-copper bonding and alignment process. This process allows for immediate circuit stacking after standard back-end processes without any additional processing steps other than CMP and surface treatment techniques to ensure good bonding conditions.
Manufacturability
To begin evaluating 3-D processes for manufacturability, Sematech (Albany, N.Y.) turned to a well-known industry cost model. "Looking at the incremental costs for doing 3-D processing forces you to think through the whole process and start putting numbers against each of the process steps," said Sitaram Akalgud, Sematech's 3-D interconnect program director. "Moreover, it may provide some insights and surprises. For example, comparisons made between 10 × 50 μm deep TSVs to those 5 × 30 μm deep showed that the costs of etching and metalizing the TSV decreased with the smaller via. This study also highlighted that the cost of depositing, etching and stripping a hard mask can be comparable to that of etching the TSVs." Although the modeled costs are not calibrated with real manufacturing data, they are useful for spotting trends.
When Sematech applied the cost model to W2W and D2W bonding, the results were unexpected. The attraction of W2W is the capability of bonding hundreds of die together in one operation, akin to the parallelism of a front-end process — a clear advantage when wafer yields approach 100% and wafer and die sizes are the same. However, Arkalgud explained, even with a slow die pick-and-place and bond process of one bond per minute, where placing 600 die per wafer can take close to 10 hours to fully populate a wafer, it still makes sense to choose D2W if die yield is &80%. It depends on the number of die per wafer. But once tests costs are factored in, "the opportunity to improve the yield is more than enough to compensate for the expense of taking this long time to assemble the whole wafer," Arkalgud asserted.
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| 4. When a cost model was applied to 3-D IC processes, costs were shown to decrease by 17% when TSV dimensions were reduced from 6 × 60 mm to 3 × 30 mm; and a depreciated toolset was shown to contribute even greater cost reductions. (Source: Sematech) |
Reliability issues are an important aspect of manufacturability that was explored at a Sematech's workshop last year. In particular, it was highlighted that the thermal coefficient of expansion (TCE) mismatch between copper-filled TSVs and silicon can lead to open vias, and the stress induced in the silicon near the TSVs can also shift transistor electrical characteristics.
Device/system design
The challenges of stacking existing die are primarily ones of adapting tools for the new technologies. However, "performing a system design across multiple die is a far bigger design issue that greatly increases the degrees of freedom," said Eric Beyne, scientific director of the Advanced Packaging and Interconnect Center at IMEC (Leuven, Belgium).
To the designer, this becomes effectively a system-on-a-chip (SoC) design at the 3-D level where the physical design aspects play a bigger role in evaluating optimum device technologies for different circuit blocks and novel high-bandwidth/low-energy interfaces to build higher-performance, lower-energy and lower-cost systems. Therefore, path-finding tools that consider theses complexities and allow for a fast comparison of different system options become crucial in making the correct choices.
IMEC is introducing software, Path Finding Flow, to simulate 3-D chip stacks including interconnects and required TSV densities, taking into consideration the cost of the process. IMEC is in the process of making Path Finding Flow available to system engineers to identify the benefits of various technologies.
IMEC is concentrating on two areas: wafer-level packaging (WLP) and stacked-IC (SIC) technologies. WLP is relatively straightforward, taking existing chips, connecting and stacking. Therefore, depending on the device, there may be little change in the design. In contrast, in 3-D SIC, the device and packaging must be designed together, creating a more complex process. However, the advantage of smaller TSV pitches and resulting higher performance and lower energy consumption and costs clearly outweigh the challenges. "3-D SIC TSV technology has the highest added value," Beyne said.
IMEC's 130 nm technology was used to form 3-D SIC via structures made on a CMOS test device. The SIC was thinned to 25 μm, stacked to a second device, and electrical connections measured from the top die to the bottom die. Considered a first for this type of high-density technology, the SICs had 5 μm diameter TSVs on a 10 μm pitch.
The only commercially available 3-D EDA software is from startup R3Logic (Waltham, Mass.). Though industry consensus is that 3-D IC is a given, thus far, major players have not been responsive to requests for such software. This must change, Garrou said, "because this industry segment will not take off without standardized widely available software."
3-D equipment
EMC-3D is an international 3-D consortium of equipment and materials suppliers that was formed in 2006 with a common goal of determining the flow that would meet the needs of a majority of device types and the fastest time to market. Earlier this year, Applied Materials (Santa Clara, Calif.) joined the ranks, working closely with other members and customers "to define and validate cost-effective process flows for 3-D IC integration," said Sesh Ramaswami, senior director and TSV program manager at Applied Materials.
TSV processing leverages front-end technologies such etch, deposition (dielectric and metal) and CMP (copper, silicon, dielectric). However, going from standard FEOL via dimensions to TSVs that are orders of magnitude larger, and to do this as inexpensively as possible, is not trivial. In etch, the challenge is to maintain a high etch rate while modifying chemistries and equipment to obtain better profiles and smoother sidewall requirements for the deeper TSVs.
Materials characterization comes into play for the deposited dielectric film to avoid crosstalk as adjacent copper-filled TSVs can act as transmission lines. Since the films must meet higher quality requirements in terms of breakdown, leakage and uniformity in step coverage, capacitance testing is critical. Therefore, while the deposition equipment remains the same, film characterization is a new and necessary condition.
Similarly for barrier seed deposition and metal fill, the cost of filling a larger via draws much of the focus. Partnering with Semitool (Kalispell, Mont.), Applied Materials is working to characterize the metal film for 3-D logic and memory structures. And again at CMP the question is asked, How do you maintain the CMP profile across the wafer, removing 10× more copper, and do it with good control and at a lower cost? Work has also begun in defect inspection to look inside the TSV after various stages in the process.
What more is needed?
One of the most important issues impacting the progress of 3-D IC technology is the lack of foundries to supply die with TSVs, Garrou said. Currently, only one foundry is targeting this goal — TSMC (Hsinchu, Taiwan) is planning to offer its iTSV capability by 2011. However, this is not hampering 3-D makers like Tezzaron, which formed an exclusive agreement in 2007 with Chartered Semiconductor (Singapore) to fabricate TSVs for its 3-D IC memory chips.
TSMC remains the key player. However, until its TSV flow is in place, worries will continue to grow. "Without access to foundry or major IDM-based die with TSV built into them, 3-D IC will simply not take off," Garrou said.
Another important aspect is the supply chain management, IMEC's Beyne noted. For 3-D stacks consisting of wafers from different sources, typically a third party, a subcontract assembly and test (SAT) company is used as integration partner because this is a more neutral partner than the fabs. The boundaries and interfaces between the fabs (which need to perform the via-first "embedding") and the SAT (which ultimately needs to perform the stacking) need to be clearly defined.
In the coming months, other technologies will need to be addressed, such as at the packaging level, wherein D2W technology is needed for transferring wafers that have been thinned on handle wafers to a flexible frame before the handle wafer is removed. Furthermore, as more functions are combined in a single chip, testing will become a serious issue where on-board testing may well become mandatory, Patti said. In the meantime, 3-D IC is clearly on the move.
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