Mentor Enhancing Yield Diagnostics Tool
Mentor Graphics is adding more powerful statistical analysis techniques to its yield diagnostics tool, Yield Assist. The diagnostics method combines the more complex, compressed data available from logic testers with information from logic netlists and design layouts. The technique can narrow down problem areas on the die, and shorten the time required for failure analysis.
David Lammers, News Editor -- Semiconductor International, 5/6/2009
Mentor Graphics Corp. (Wilsonville, Ore.) is adding statistical analysis techniques to its yield diagnostics tool, Yield Assist, that will provide semiconductor manufacturers with faster yield ramps and less onerous failure analysis (FA) costs.
Speaking at the EDA Tech Forum in Austin, Texas, Brady Benware, engineering manager of the diagnosis/yield group, said Mentor is in the beta stage of rolling out an enhanced version of the tool, which adds deeper statistical analysis to failure data. Benware said the race is on by the major EDA vendors and some startups to provide more powerful statistical-analysis diagnostic tools, which combine information from test patterns, layout-aware information, and design netlists.
Although the downturn has somewhat delayed the uptake of the newest and more intelligent automated test equipment (ATE), Benware said the latest generation of testers provides compressed failure data that can be used to greatly narrow down the probable causes of devices failures.
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| Yield diagnostic tools can narrow down likely defects and areas on the die, reducing the time needed for failure analysis. |
At the forum, he described several examples of how diagnostic information can be used to narrow down problems, reducing the probable location of the fault to a small segment on a die so that the FA process can be shortened to days instead of weeks. “Diagnosis is still a process by which we say here is a list of the possible things that could be wrong,” Benware said. “It is like looking for a needle in the haystack, where we can now say we have found a few needles, but we don’t know which one is the problem. Diagnosis may never get to the point where we know exactly what is wrong on every single device. But it can provide a small list of things which may be wrong.”
The traditional flow of information from the fab back to the yield engineering team has been hampered by the rise of fabless and fab-lite companies relying on foundries, which may be reluctant to provide information. At the same time, FA techniques are becoming more complex, and sample preparation takes a much longer time.
Mentor has been working more on its diagnostic tool effort, as the technique gains adoption by the major logic vendors, Benware said. Although some IDMs maintain internal diagnostic tools, others are turning to Mentor for the diagnostic tools that add statistical analysis techniques, he said.
Statistically enhanced diagnostic tools also can provide feedback to the design for manufacturing (DFM) effort, helping to prioritize whether a company’s DFM tools should emphasize lithography restrictions, CMP rules, or others. “DFM is one of the real challenges,” he said. “Amongst all the things recommended, it is difficult to prioritize the different fixes to design, or to quantify the impact as we do fixes. If we understand well what the defect distribution is, we have a better chance to prioritize DFM fixes.”
The goal is to correlate test results with information from the design process to understand the root cause of problems. Future directions include adding other kinds of analysis, based on power droops or antenna issues.
For now, the diagnostic techniques provide a narrowing-down process, much like a police detective might examine dozens of video tapes of bank robberies to create a narrowed-down list of images of possible suspects. Benware provided an example of a logic net with 99 signal lines spread across 14 segments, in an area of the die 1200 µm2. By using layout information, the problem was narrowed to one of eight branches. The technique was able to further narrow down the problem to one failure type: an open in one of the interconnects. “By eliminating the 99 bridges, we could reduce the problem to only one segment out of the original 14, and the process reduced the suspect area by an order of magnitude,” he said.
Transcript: When Design, Yield, FA Intersect
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