Achieving Superior Interconnect Reliability at 65 nm and Beyond
Engineers are meeting reliability specifications despite scaling’s ongoing implications and the incorporation of more porous low-k materials.
Laura Peters, Senior Editor -- Semiconductor International, 11/1/2006
The ongoing scaling of VLSI circuits, particularly high-performance logic devices, drives the need for low-k materials and copper interconnects to reduce resistance-capacitance (RC) delay, cross-talk noise and power dissipation. With scaling, and particularly the incorporation of low-k materials with weaker breakdown strength than SiO2, the challenge of producing reliable multilevel interconnect stacks becomes tougher. Reliability lifetimes of electromigration (EM), stress migration (SM) and low-k time-dependent dielectric breakdown (TDDB) must meet stringent targets.
Despite the challenges, some argue that interconnects are as reliable as ever. “People are now ramping their products faster, to production yields of 90% or better, within a matter of months, whereas at one time this took a year to a year and a half. Part of the reason is the maturity of the copper interconnect technology and the extensive learning that went into the 130 nm and 90 nm devices,” said Chris Case, chief technology officer of BOC Edwards (Wilmington, Mass.) and co-chair of the interconnect technology working group of the International Technology Roadmap for Semiconductors (ITRS).
Still, with scaling, nearly every aspect of reliability performance gets tougher. “The reliability problem is not about electromigration or stress migration per se. There are other problems arising from process-induced defects due to the thinner barriers and ultralow-k dielectrics, and interfacial delamination due to chip-package interaction, which inherently come with scaling,” said Paul Ho, professor of material science and engineering at the University of Texas at Austin. He also expressed concern over the ability to maintain the desired bamboo structure of the copper in dual-damascene interconnects with very narrow dimensions. “The change in the copper microstructure with scaling can degrade the lifetime statistics of copper interconnects, which can significantly affect the extrapolated lifetime at operating conditions. This problem is seldom addressed by the industry.”
TDDB
With SiO2 intermetal dielectric, TDDB was of little concern. Now that low-k films have replaced SiO2, TDDB has become more critical. TDDB is the time needed to break down an oxide by prolonged high-voltage stress. TDDB stresses can be used to estimate product lifetime.
The most widely used first-generation low-k material, SiCOH, has advantages, including a relatively high-dielectric strength (8-9 MV/cm vs. 11 MV/cm for SiO2 and 3-4 MV/cm for polymer dielectrics). SiCOH supports only a low concentration of copper atoms in the dielectric, making it fairly resistant to dielectric breakdown. However, this is only the case for the dry, bulk film. Once integrated and exposed to plasmas and water, catastrophic copper leakage paths can form.
There is also new insight into the mechanism of SiCOH dielectric breakdown, which indicates enhanced margin for TDDB than was previously predicted by accepted models. “People were really struggling to meet their requirements using the linear extrapolation law. But if they use the square root model, they gain about two orders of magnitude of margin,” noted Glenn Alers, principle engineer at Novellus Systems (San Jose).
The new field-acceleration model has been derived by researchers at IBM based on extensive experimental data and failure analysis results. Led by Fen Chen of IBM Microelectronics (Essex Junction, Vt.), and using the square root of electric field (√E), the model correlates better with TDDB data taken over longer than a year than either the E model or 1/E models (Fig. 1), the two main field-dependent TDDB models currently in widespread use. As explained in a more detailed paper,¹ the origin of √E relation to TDDB is caused by the current conduction mechanism of SiCOH dielectric film under electric field. As a result, Chen and colleagues proposed a fluence-driven, copper-catalyzed TDDB model.
|
|
1. Field-acceleration data with various models for a comb-serpentine device at 150°C. The √E model correlated best with the data. (Source: IBM)
|
This model postulates that accelerated electrons injected from the cathode follow interface Schottky Emission or Poole Frenkel conduction during transport at the SiCOH/cap interface. Some electrons will undergo “thermalization” under high-field and high-temperature conditions, and these electrons can impact copper atoms at the anode and accelerate the generation of positive copper ions when they reach the anode. Those generated ions can then inject into the dielectric under the field along a fast diffusion path, such as the SiCOH/cap interface. Migrated copper ions recombine with electrons to become copper atoms. Two possibilities of SiCOH breakdown are possible after a concentration of copper in SiCOH reaches a critical level: Copper atoms form clusters that connect to create a direct metallic shorting bridge or cause local dielectric thinning to trigger an electrical short. Or the diffused copper atoms catalyze the bond-breakage reaction of SiCOH because of their relatively large atom size, enough to induce permanent SiCOH bond displacement. Applied high field enhances the copper ion generation by supplying infinite copper source at the anode, and enhancing diffusion toward the cathode.
|
| 2. The post-TDDB fast diffusion path along the SiCOH/cap interface allowed copper ion diffusion. The metal bridge resulted in a resistive short. (Source: IBM) |
Chen’s studies further showed:
-
SiCOH TDDB is sensitive to all aspects of integration.
-
SiCOH breakdown appears to follow a three-step, electrochemically based model.
-
Field, temperature, moisture and oxidized copper drive copper ionization.
-
Copper likely migrates along the SiCOH/cap interface (Fig. 2 ).
Because failures occur at the interfaces, interface control is the name of the game. “Making robust interfaces always gives you more margin,” said Ken MacWilliams, vice president of Applied Materials' Dan Maydan Technology Center (Santa Clara, Calif.). “Also, because lines are getting thinner, any line thinning can have an effect on current density, affecting reliability.” MacWilliams also added that electrochemical mechanical planarization (ECMP) processes are a critical process in controlling dishing, erosion and line-dimension uniformity.
Low-k damage is also being controlled by less damaging etch processes and downstream plasma precleans, especially prior to barrier deposition. There is more widespread use of hard masks for patterning, which also helps control the sidewall roughness of the dielectric.
Since TDDB has become so critical, the optimization of low-k processing has largely focused on maintaining k value and mechanical/electrical properties throughout processing to assure packaged device reliability.² “A lot more concern is paid to how these films are passivated, especially for porous low-k,” Alers said. “Around each die and around each tester, engineers are also using a guard ring to prevent the films from absorbing water.” One of the downsides to using this type of guard ring is that it can crack during the dicing process.
Beyond the compromised mechanical and electrical strength of the dielectric, the impact of Joule heating becomes more significant with low-k films because of the poorer thermal conductivity. Of course, the temperature rise is most severe at the upper levels of metal. Most designers cannot push the maximum current density (Jmax) beyond current levels of ~0.5-2.0 MA/cm², because Joule heating occurs at 2-3 MA/cm².
Electromigration
EM is the migration of metal atoms in a high-current-density carrying line caused by momentum transfer from conducting electrons. In copper interconnect systems, EM is driven by interface and surface diffusion. This is very different from aluminum/oxide-based systems, where the primary cause of aluminum EM was grain boundary diffusion. Copper interconnects exhibit bimodal failures — with the early failures dominated by void formation at the via-bottom interface, and late failures the result of voiding in the line. The weak mode relates directly to the copper/barrier interface quality.
In dual-damascene interconnects, the high-aspect-ratio vias have been recognized as the most complicated region for integration, and reported as the weakest link for reliability purposes. There are intrinsic reliability issues where it is understood the EM lifetimes are proportional with linewidth scaling. Extrinsic EM reliability issues arise from any number of process-induced defects. Many relate specifically to the via barrier, and can manifest as poor adhesion, integrity, mechanical strength and uniformity of the via barrier. Optimization of via processing, including via barrier coverage, barrier etch and via cleaning processes, are therefore areas of great focus. “There is more and more evidence to suggest that, as linewidths reduce and barrier layers are scaled down, there are increasing problems with process-induced defects,” Ho said.
Non-uniform barrier coverage is a common cause of EM early failures. The physical vapor deposition (PVD) barrier process can suffer from a shadow effect, where the barrier deposits non-uniformly in the via. The amount of barrier deposited is a function of the spread of the approach angle of the PVD barrier beam reaching that via sidewall. Researchers at Texas Instruments tested the effects of different barrier processes on EM reliability.³ They used dual-damascene copper test structures in low-k organosilicate glass dielectric (k=2.8), with Metal 1 (M1) and Metal 2 (M2) widths of 0.09 and 0.1 µm, thin tantalum barriers on the sides and bottom, and SiCN dielectric caps on top. EM testing was performed at 250, 275, 300 and 325°C, with current density of j=1.0, 1.5, 2.0 and 10.0 MA/cm². Failure occurs with the initial step in resistance. Some failures were caused by non-conformal barrier coverage because of PVD shadowing. A critical amount of barrier deposition is needed to eliminate a weak point in the via barrier. Minimum thickness turned out to be more important than average thickness.
If the via-bottom interface quality is poor and has a low diffusion activation energy, a thin void will grow along the via bottom interface and cause a failure in a short time (Fig. 3b). Copper ions under long EM stress travel toward the anode along the interface between the copper (M1) and the SiCN cap, which is the fastest diffusion path. The migration is slower at the cathode via-bottom interface between the tantalum in via 1 and copper in M1 because metallic bonding normally has a higher activation energy. The void nucleates where the Cu/SiCN interface meets the Cu/Ta interface (Fig. 3c). The cone-shaped via (Fig. 3d), which has undergone more extensive argon resputtering to achieve via punchthrough than the flat vias shown in Figures 3a-c, forms a full-span void in the same place as the flat-shaped via (Fig. 3a ). Ki-Don Lee and colleagues at TI concluded that the key factors to control EM reliability are via barrier coverage and via-bottom interface quality. These hurdles are overcome by process optimization.
|
|
3. Electromigration-induced voids formed as full-span void under a flat-shaped via (a), thin void responsible for short EM lifetime (b), flat via showing void nucleation at the corner (c), and a full-span void under a cone-shaped via (d). (Source: IEEE/IRPS)
|
Barrier quality is also being improved in terms of attaining a more nano-crystalline structure. “We’ve done a lot of work that has resulted in very thin barriers of 30-40 Å that have the properties that once belonged to a 200 Å barrier. Weakness of the barriers, especially in the corners, has also been addressed,” MacWilliams said.
In order to improve EM performance, much work goes into improving the interface between the copper line and overlying dielectric cap. For instance, new self-aligned CuSiN processes have been developed by researchers from NEC Electronics (Kanagawa, Japan)4 and the Crolles2 Alliance (Crolles, France)5 to enhance reliability. These processes were developed in lieu of selective cobalt capping processes, which require an extra pre-clean and plating step.
Briefly stated, both the Crolles² (Fig. 4 ) and NEC selective copper nitride processes involved three main steps: a reducing plasma to convert copper oxide to copper; silane gas exposure to diffuse silicon into the copper; and a nitrogen-containing plasma to scavenge excess silicon and generate Si-N bonds. Next, plasma SiC is deposited using a complex organic methylsilane source.
|
|
4. CuSiN/SiN bilayer simultaneous formation mechanisms during CuSiN process and the accompanying TEM cross-section. (Source: Philips Semiconductors Crolles R&D)
|
Work headed by Laurent Gosset of Philips Semiconductors (Crolles, France), together with colleagues from STMicrolectronics, Freescale Semiconductor, Philips Research (Leuven, Belgium) and CEA/LETI (Grenoble, France),5 compared several ways of achieving self-aligned barrier integration using copper-line surface treatments. This process was found to provide a better barrier to copper diffusion and oxidation. The researchers proposed that the mechanism may be caused by the formation of an ultrathin SiN film above the modified copper surface during the sequence. A key advantage to the process is its direct compatibility with existing plasma-enhanced chemical vapor deposition (PECVD) processes and tools.
Tatsuya Usami and fellow researchers at NEC realized a 39× improvement in via EM and 1.5× better time-zero dielectric breakdown (TZDB) using a SiC-based barrier (k=3.5) vs. a SiCN barrier (k=4.9) with a baseline ammonia pre-treatment. The study showed that the CuO reduction was related to the improvement in via EM performance, and the nitrogen-rich interface was related to improved TZDB.
CoWP capping layers have demonstrated that they can provide 10-40× improvements in EM performance. However, the manufacturability and cost of the process have not yet warranted its implementation in manufacturing. “Cobalt capping substantially improves electromigration reliability, everyone agrees, but it’s an additional process step. The reality of the economics is that the ROI to add a step to improve reliability is not there,” Alers said. Integration issues remain with CoWP capping as well, such as selectivity loss, which leads to leakage current concerns. There is also the problem of dealing with unlanded vias.
There are also alternatives, such as aluminum capping, which may be as effective as the CoWP cap layer, but may not be as far along in the development. “The industry is exploring other cap layers and some seem to be effective, but the question is how to effectively implement them,” Ho said.
Though the copper line/cap interface is important, it’s not the only interface of concern. In fact, with scaling, the benefit from a modification such as cobalt capping is reduced. “The benefit becomes lessened as you scale the via because the volume is reduced, so the volume-to-surface ratio changes, making the sides just as important,” Case said.
Stress migration
With scaling, SM that results in small voids in vias becomes more common because fewer vacancies are required to cause an unacceptable rise in via resistance. Typically, SM has been most prevalent where single, medium-sized vias are connected to wide copper lines, but recently they have been reported for narrow metal leads as well. The voids are caused mainly by copper’s larger coefficient of expansion relative to that of the interlevel dielectric. Copper has a lower activation energy for diffusion into the dielectric layer than aluminum, so copper atoms diffuse at higher rates.
One commonly implemented solution to SM problems has been via doubling. “Design rules play a big role in stress migration. People tend to have hundreds of different stress migration test structures with different design rules, slabs of copper and narrow lines to cover all the possibilities,” Alers said.
Future directions
It appears that, so far, reliability issues have not stopped IC manufacturers from meeting performance and time-to-market goals. But necessary scaling is affecting the way EM, SM and TDDB are managed. “It used to be you would push the technology for as low an RC as you could and reliability would just happen,” Alers said. “But now, reliability is beginning to impact performance. For instance, we can improve reliability by making the copper barrier/liner thicker, but that comes directly with a cost of linewidth and resistance.”
It is also possible that problems like power dissipation will require more radical solutions. Beyond such measures as microfluidic cooling or microchannels may be the bolder move to chip cooling. Since PC and game chips currently run at ~100°C, cooling can provide reliability benefits. “Cooling chips to sub-ambient levels has been used on supercomputers, and it might find its way to more mainstream applications,” Case noted.
Exploring Advanced Interconnect Reliability
03/13/2010
