TSMC Unveils 45 nm HP Process at IEDM

David Lammers, News Editor -- Semiconductor International, 12/12/2007

Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC, Hsinchu, Taiwan) came to the International Electron Devices Meeting (IEDM) with a presentation on its 45 nm high-performance process, which moves into early production next May.

With a growing band of companies — including cell phone, graphics, and field-programmable gate array (FPGA) IC vendors — pushing TSMC to higher performance levels, the company’s technology attracted close attention at the IEDM meeting.

The TSMC 45 nm paper — presented by C.C. Wu, deputy director of logic technology development at TSMC — was first up Tuesday (Dec. 11) morning, preceding the highly anticipated Intel (Santa Clara, Calif.) paper on its 45 nm process, the first to market with a high-k/metal gate (HKMG) approach. With the IBM-led Fishkill, N.Y., alliance absent from the heavily attended session on advanced CMOS (IBM and Advanced Micro Devices [AMD, Sunnyvale, Calif.] presented their 45 nm process last June at the Symposia on VLSI Technology and Circuits in Kyoto, Japan) that shifted the spotlight to TSMC’s presentation.

While the TSMC 45 nm process eschews HKMG technology, it uses “the most aggressive design rules in the industry,” Wu said, achieving a poly contact pitch of 162 nm, nearly the same as the 160 nm pitch reported by Intel Corp. With immersion lithography driving such aggressive design rules, Wu said TSMC engineers worked hard on overlay control, which he said is “very important to have good yields.” The 45 nm process yields a gate density that is 2.43× higher than that of the 65 nm process. The gate length is 30 nm, and the SRAM cell size is 0.242 µm^2.

TSMC adopted embedded silicon germanium (eSiGe) in the PMOS transistors, striving to achieve good SiGe proximity to the channel and moving to a higher annealing temperature.

TSMC added embedded silicon germanium (eSiGe) at the PMOS side to improve hole mobility in its 45 nm technology.

To reduce overall capacitance, TSMC used an interconnect dielectric with a k value of 2.55 from the top metal layer down to the first metal (M1) layer. Because delays from increased wiring capacitance are increasing with each generation, Wu said to achieve a 20% overall performance gain, the transistor front end must be improved by 35-40% with each generation to compensate for the slower back-end-of-line (BEOL).

TSMC used an oxide poly gate stack with a 12.5 Å equivalent oxide thickness (EOT) rather than the HKMG approach. However, polysilicon depletion adds as much as 6 Å to the gate oxide thickness. Wu said TSMC’s evaluation is that device leakage continues to be “dominated by subthreshold leakage” rather than gate leakage.

Carlos Diaz, director of logic research and development at TSMC, said, “When you look at power vs. speed, the performance delta [between the HKMG and oxide poly gate stacks] is not that large. It depends on the application. And when it comes to cost, we want to stay on the conventional curve.”

Y.J. Mii, the 45 nm program manager, said, “High-k does provide some advantage in terms of performance. From our estimation, high-k provides about a 10% performance gain,” but at the impact of additional cost and process complexity.

“A thinner EOT for the next generation [32 nm] is going to help. We have a very aggressive back end [at the 45 nm generation], so we should a better density than other companies. That will help our customers,” Mii said.

Scott Thompson, a professor at the University of Florida (Gainesville, Fla.) who chaired an IEDM Sunday short-course session on CMOS technology, said TSMC’s oxide poly gate stack “is very comparable to HKMG. It is on par. The jury is still out on how much performance boost HKMG provides. And TSMC, for the first time to my knowledge, did something that does provide a big performance increase — it implemented epitaxial strain” in the pFET transistor.

As for leakage, Thompson said he agreed with Wu’s assessment. “Most chips still are source/drain leakage dominated.”

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