Jeffery Butterbaugh, Chief Technologist, FSI International
Alexander E. Braun -- Semiconductor International, 5/1/2006
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| Jeffery Butterbaugh (Source: FSI International) |
Jeffery Butterbaugh is the chief technologist for FSI International (Chaska, Minn.). He joined the company in 1993 to lead process development for photochemical wafer cleaning. From 1995 to 2001, he was an engineering manager and led process development teams for anhydrous HF, cryogenic aerosol, and immersion processing, as well as spray acid processing. Prior to FSI, Butterbaugh worked as a photolithography process engineer and a plasma etch development engineer for IBM (Burlington, Va.), and as a sputter deposition and sputter etch engineer for Seagate Technology (Bloomington, Minn.). He currently serves as co-chair of the Front End Processes Technology Working Group for the International Technology Roadmap for Semiconductors (ITRS). Butterbaugh has a Ph.D. in chemical engineering from the Massachusetts Institute of Technology (MIT) and a B.S. in chemical engineering from the University of Minnesota. He holds eight U.S. patents, and has authored or co-authored more than 40 papers on surface conditioning and plasma etching. FSI International offers surface conditioning technology solutions.
SI: How do you see your role in an industry that's changing so rapidly in its use of materials and architecture designs?
Butterbaugh: My role as chief technologist at FSI is to track what's happening with surface preparation technology and chart our roadmap for future products and development efforts, which means I must be aware of our customers' roadmaps as well. I understand their goals by meeting with them and listening to what they have to say, and by attending or reading as much as possible about what they present at conferences or in published papers. Thus, we can determine where they're headed and what surface prep technology we need to supply to meet their needs. It's helpful for us to identify and understand what they view as roadblocks, to determine how our technology can be a fit, and to see if we already have a solution that they can use, or we have something that can be adapted, or whether we need to develop something new.
SI: So it's a marketing and technical proposition?
Butterbaugh: Yes. It requires understanding the market pull from the customer's perspective, as well as what technologies are being developed — at the university level, for example — which may not yet have a connection to commercialized technology. So I look at fundamental technology and try to determine if there is a linkage that I can then bring to our engineers and engineering managers who will eventually have to make it work.
SI: So you keep an eye on technology in use as well as what might be coming out from academia?
Butterbaugh: Yes, and sometimes that's difficult to do. As with any engineering or technology company where people have several roles, day-to-day requirements get priority: delivering systems, addressing customer needs, or working on projects to close on sales. I sometimes must participate on teams to address these day-to-day challenges, and it's sometimes difficult to keep focus on future strategies and product development. But it is important to keep an eye on what's happening at universities and in the industry at large, in case there is a solution that is connected to a current need, and also to help steer efforts toward what we see as future challenges.
SI: So what's happening in the area of surface preparation?
Butterbaugh: For the last few years we've been seeing an increasing need in surface preparation — selectivity. In the past, IC manufacturers and cleaning companies have been able to sacrifice some of the desired device structure or films on the surface in the cleaning process to get wafers as clean as possible. We've been seeing an ongoing tightening of this window, trying to maintain cleanliness metrics to make wafers as clean as possible without touching the device or the materials and structures on the surface. The first thing to look at is what you're already doing and try to tweak or optimize it. Another option is to look at the overall integrated process to see if there are sequences that can be changed or eliminated that may be damaging, then come up with an approach that is both evolutionary and results from studying the integrated process to determine whether the mindset can be changed. This often originates from the IC manufacturer as well as the supplier simultaneously recognizing the need.
SI: New materials complicate this.
Butterbaugh: Definitely! First it was the BEOL with copper and low-k introduction, now it has shifted to FEOL with high-k and the introduction of new metals. There are many things that previously we wanted to keep away from the device. Nickel, for example, is an issue in the gate oxide and you didn't want it there because it ruined the device. Now we're purposely putting it in the source and drain to improve resistivity. Coming up with wet processes to deal with these materials and keep them where they're supposed to be results in critical selectivity challenges where you must remove some materials and leave others. Gate stack integration, surface preparation and wet etching are all things IC manufacturers are now struggling with.
SI: From the device maker's perspective, what's the biggest cleaning nightmare?
Butterbaugh: Damage-free cleaning is at the top, which encompasses etch loss as well as physical damage. Right behind that are issues with the wafer's edge — defects generated there are making their way into the device area. So you've defined an edge exclusion and do not really need that area to yield devices; however, by not controlling what goes on at the edge of the wafer, you can generate defects that migrate onto the wafer.
SI: Is this exacerbated by shrinking exclusion zones?
Butterbaugh: DRAM manufacturers, particularly, are trying to migrate to the edge. However, this might help because if we could do without an edge exclusion and use the entire wafer, then maybe the processes could focus more on obtaining better results at the edge or reducing problems generated at the edge.
SI: How do these changes and requirements affect your R&D philosophy?
Butterbaugh: You want to have solutions ready when the question comes up. It would be ideal if when someone came up with a new challenge you had an answer ready to go, but you always have a cost issue — you want to ensure that you're not spending money on something leading nowhere. There is considerably more focus on being as market-driven as possible that is basing R&D on very well defined needs for the future. This philosophy is reflected in how we approached the bubble of interest in supercritical CO2 a couple of years ago. We really listened to what the end user was saying about the applications they believed were going to be key drivers. While closely studying what was going on with SCCO2 technology and its potential for meeting future challenges, we also focused efforts on how to evolve our current technologies to meet those needs, and we were successful in doing so. One focus of SCCO2 development was porous low-k integration for metal interconnects. We were able to show feasibility for using current surface preparation technologies to meet the challenges of porous low-k integration. As it has turned out, because of many other integration issues, porous low-k keeps being pushed out in the roadmap, the supercritical CO2 boom went bust, and many companies stopped their investment in it. The pull wasn't there to justify the cost of introducing and manufacturing that new technology. Thus, part of our philosophy is to get the timing right and spending resources on technologies that have an introduction pathway to manufacturing, and to expand current platforms, whenever possible, instead of trying to introduce radically new technologies. This helps economically both our customers and FSI.
SI: The new ITRS plots a difficult road for OEMs; there's no shortage of hurdles. A corollary of this is that R&D costs are getting increasingly higher. How do you meet this problem?
Butterbaugh: We're spending more of our development time in partnerships with end users. This is really the only way for us to economically accomplish R&D. Some larger suppliers have completely outfitted their applications labs to do all the processing steps to get a baseline from which to work. While in our Class 1 lab we have our most advanced platforms and have invested in state-of-the art analysis and metrology equipment to characterize our equipment and processes, we cannot afford to build our own mini IC fab, so we rely on customer partnerships to get wafers and research materials to do early research, and then quickly move equipment at the alpha or beta stage into their facilities. The end user also can see a real advantage in this, since we provide equipment for an evaluation period and then closely work with them in their fab to integrate and optimize the process into manufacturing. FSI's expectation is that our solution will become key to their manufacturing processes.
SI: Aren't there risks with this?
Butterbaugh: Yes, you'd like to have everything tested and developed before it goes out to the field. Also, it can dilute your IP somewhat — if new ideas are generated in the field, they may end up being jointly owned. However, many companies lack the capital to completely prove out a technology before introducing it to the end user. Partnering with consortia, such as Sematech and others, as well as working with government labs, is also useful.
SI: Is your latest product a result of this kind of R&D effort?
Butterbaugh: Yes. We've optimized a segment of the cleaning process by studying how the process is integrated in our customers' fabs, and then working with them to further develop the new approach. Specifically, in this process we're focused on resist stripping. For the past few years, to address the problem of controlling material loss during the cleaning process, we worked on our post-ash cleaning step and tried to optimize it — maximize the cleaning, minimize the material loss — while accepting the fact that some ash steps will always come before. Through conversations with our customers, we decided that, if we could eliminate the ashing step and expand the role of wet clean to include bulk resist removal, we might be able to get a better handle on overall material loss. To do this, we had to understand what limited our ability to strip implanted photoresist, and went back to the lab to try to improve the wet process and expand its capability to remove implanted photoresist. As a result, we can now wet strip a majority of the implanted photoresist levels without ashing. In addition to addressing some of the material loss issues, we believe it will improve productivity for IC makers by removing a step and simplifying the process.
SI: In general, how do you view the industry-wide R&D effort?
Butterbaugh: As far as the IC industry is concerned, it appears adequate to the needs. However, one area of upcoming concern is the future need for 450 mm wafer processing. It seems we're inside the development lead time for the ITRS-predicted manufacturing need in 2012. In general, there's money to explore things beyond just what's needed at the moment. For decades, it's been the industry's nature to find a solution and put it to work before really understanding all the fundamentals, which can sometimes put you in a space where you don't want to be. If I were to have more funding for anything, it would be to spend more resources doing more methodical research to better understand and explain why some of the current solutions work the way they do, and then find a way to extend these solutions into the future.
