Industry News: WLP Trends; Solar Fab Process Control; Lanthanum Doping
Staff -- Semiconductor International, 2/1/2009
Wafer-Level Packaging Trends Up in 2009
Driven by increasing demand from mobile devices and automotive applications, wafer-level packaging (WLP) is moving up to higher I/O counts and finer pitches, experts said. Other WLP trends to watch in 2009 include high-power and high-accuracy precision devices, through-silicon vias (TSVs), fan-outs and embedded flash.
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| Demand for wafer-level packages is being driven by portable systems. |
John Hunt, director of engineering at Advanced Semiconductor Engineering (ASE, Taipei, Taiwan), said the demand for WLP is increasing as new designs target WLP solutions. As demand for smaller packages with higher I/Os increases, Hunt said WLP will gradually take market share from legacy packages, including BGAs and leadframes.
WLP can be considered a subset of the flip-chip package category, with a somewhat larger pitch and larger solder balls.
Hunt said portable devices are the market driver for WLP because of its advantage in size and weight, as well as electrical performance. "We're also seeing an increase in automotive applications because of the increased complexity in cars today," he said. "But the large volume of products that ASE and others are producing is for handheld devices like mobile phones, games, PDAs, cameras and other types of devices where consumers are looking for a smaller device to put in their pocket and carry around easily. The electrical performance translates to higher frequency — you get less noise and lower parasitics, so you get a slight increase in battery life. And we all want our portable devices to last longer on a battery charge."
Jan Vardaman, president of packaging consultancy TechSearch International (Austin, Texas), said the hot topic for WLP in 2009 is fan-out packages. "The industry will see some of the first commercial adoptions of new versions of these fan-out packages in 2009 for mobile phone applications."
— Sally Cole Johnson, Contributing Editor
Solar Fab Process Control Software Saves Time and Money
Rudolph Technologies Inc. (Flanders, N.J.), which specializes in process characterization solutions for the semiconductor manufacturing industry, has made its way into photovoltaics fabs with Discover Solar, a fab management software tool designed to help PV manufacturers increase cell efficiency and reduce costs.
Reengineered for the PV industry from the company's Discover Enterprise, the software provides comprehensive analysis of process performance information to improve energy conversion efficiency of solar cells. It also enables process engineers to monitor the health of a complete production line and quickly identify tool and subcomponent problems or incoming material issues.
Manufacturing data, in actuality, does not exist in the solar world the way it does in the semiconductor world. PV manufacturers are dealing with entirely different economic and throughput models — producing as many as 500,000 solar cells a day at a cost of perhaps $5 each, compared with a big semiconductor fab producing some 100,000 wafers per month with a considerably higher value placed on each wafer. Solar cell manufacturers are trying to move those wafers through the line quickly, and the cost of inline metrology is not a worthwhile value proposition.
Therefore, solar cell manufacturers have essentially been running blind, said Mike Plisinski, vice president and general manager of the company's Data Analysis and Review Business Unit, and Discover Solar gives them some eyes.
— Aaron Hand, Executive Editor, Electronic Media
Lanthanum Doping May Boost Silicon FETs
Strained silicon has picked up the slack left from a slowdown of pure device scaling over the past decade, but the gains from strain may be reaching a saturation point, according to Dimitri Antoniadis, a professor at the Massachusetts Institute of Technology (MIT, Cambridge, Mass.). The small footprint of scaled-down devices is leaving less room for stressor materials, and it is becoming more difficult to transfer stress into the channel, he said.
Raj Jammy, director of the front-end program at Sematech (Austin, Texas), said Sematech has a focus on adding lanthanum to the hafnium-based high-k dielectrics now used in silicon devices. Sematech has paid particular attention to the reliability aspects, he said. "If you are not careful how you do the processing, the presence of lanthanum degrades the reliability slightly. If you have careful control of how you add the lanthanum, then reliability can be as good as conventional silicon dioxide."
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| Demand for wafer-level packages is being driven by portable systems. |
Lanthanum is used for Vt control. "Adding lanthanum helps you to get an nFET-like Vt," Jammy said. With heat treatment of a lanthanum capping layer, the lanthanum atoms go down into the bulk of high-k materials, creating a charge orientation or dipole that changes the barrier height. "With an nFET-like barrier height, we can get an nFET-like Vt. Adding lanthanum is an elegant way of controlling the Vt."
However, adding too much lanthanum can cause the lanthanum atoms to collect at the interface, causing charge trapping. Sematech researchers have developed a nitridation process at the interface to control the lanthanum. Sematech also is working to grow a very thin layer of germanium on top of a silicon channel to boost performance of the pFETs, and to gain better control of the pFET Vt variability.
— David Lammers, News Editor
