High-Resolution Mapping Detects Implanter Failures
Alexander E. Braun, Senior Editor -- Semiconductor International, 7/1/2007
Device linewidth and layer thickness are nearing the point where implant metrology equipment capability is limited in directly monitoring the uniformity of dopant placement across the wafer. Meanwhile, feature shrinks and parametric performance requirements have tightened process windows for critical implant parameters, while beam current and wafer size have increased. As a result, conventional methods for quantifying implant-doping uniformity across the wafer by a measured average and standard deviation (SD) — or distribution spread — lack the statistical information needed to monitor the implant process.
Work by Kendra Gurcan at National Semiconductor (South Portland, Me.) and colleagues from QC Solutions (Billerica, Mass.), addressed this problem as a result of a failure in the scan arm system on a medium-current implanter.1 The medium-current implanters already had a routine tool qualification in which a test wafer was implanted at medium scan speed and measured on the company's ICT300. Using the implant conditions of the existing qualification, tests were carried out at different mechanical scan speeds — medium vs. fast scan — to aggravate the problem with the scan arm system and highlight the problem in a post-implant measurement. The group applied high-resolution mapping techniques using surface photo voltage response (SPV). This enabled them to distinguish 2-D spatial uniformities unresolvable by traditional average and SD statistics, and observe a spatial distribution in the wafer map, which showed striping perpendicular to the mechanical scan direction of the wafer.
The next step was to determine a quantitative way of detecting the problem. This required the development of a new test procedure and a new measurement pattern, where measurements took place in a stripe across the center of the wafer to obtain a cross-section of the non-uniformity. "These mean and center deviations were used as the basis to notify of any future scan system failures," Gurcan said. "End-of-line electrical test and parametric sort data showed a spatial distribution of device failures associated with a problem implant feature, as distinguished in the wafer map by SPV." These defects can be monitored in real time using high-resolution SPV wafer mapping with a micro-uniformity statistical evaluation of the data to analyze a selected spatial pattern oriented along the implant slow-scan axis (Figure ). This analysis, along with high-resolution wafer mapping (>1750 points/wafer), allows for the daily monitoring of the known implant failure mode before end-of-line electric test or sort parametric mapping. This testing procedure is not done on production, but on test wafers. It is carried out on a routine basis by the manufacturing personnel to monitor the performance of the equipment.
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End-of-line electrical test and parametric sort data show a spatial distribution of device failures associated with a problem implant feature, revealed by surface photo voltage response (SPV) on a wafer map. These “killer” features are monitored using high-resolution SPV wafer mapping with a micro-uniformity statistical evaluation of the data. Micro-uniformity is monitored by analyzing a selected spatial pattern oriented along the implant slow-scan axis, as shown. (Source: National Semiconductor)
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Until now, there has been no other method to detect this failure mode. Aside from the QCS implanter qual, a standard resistivity qual was also used, which was unable to detect the scan system failure when it occurred. It took about two months of testing various schemes before coming up with the final concept. The first stage consisted of determining which scan speed would be best to see the non-uniformities that resulted from the implanter scan system failure. The second was an effort to determine a quantitative way that would provide a signal when this kind of problem arose, rather than just a spatial pattern on the wafer. A quantitative measured or calculated value that would flag the manufacturing floor that there was a problem with the implanter was required.
At press time, this new measurement procedure was already in use, detecting scan system failures on medium-current implanters and picking up where previous testing left off.
| Reference |
| 1. K. Gurcan, A. Bertuch and K. Steeples, "Real-Time High Resolution Wafer Mapping for Advanced Ion Implant Process Control," Frontiers of Characterization and Metrology for Nanoelectronics Intl. Conf., 2007. |
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