How Intel Made CMP Work for High-k
Joe Steigerwald, director of CMP technology at Intel, described the CMP process improvements necessary for replacement metal gate (RMG) processing. "Gate height control was the area where we struggled the most," he said in an invited speech at the International Electron Devices Meeting (IEDM) in San Francisco. Reducing defectivity levels was another challenge. He called on pad and slurry suppliers to speed up their development cycles.
Laura Peters, Editor-in-Chief -- Semiconductor International, 12/18/2008
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Intel Corp. (Santa Clara, Calif.) said its introduction of a high-k/metal gate technology at the 45 nm node depended on the development of two types of robust, cost-effective chemical mechanical planarization (CMP) processes — one to polish the interlevel dielectric through the poly gate prior to poly etchback (poly opening polish), the other to polish the metal gates.
At the International Electron Devices Meeting (IEDM) in San Francisco this week, Joe Steigerwald, director of CMP technology at Intel’s Logic Technology Development Center (Hillsboro, Ore.), described the improvements to traditional CMP processes that were necessary for replacement metal gate processing, used at the 45 nm node to create the high-k/metal gate stack. “Gate height control was the area where we struggled the most,” he said. “We had control thickness on the nanometer scale, whereas in the past it was in the hundreds of nanometer range.” Beyond the incredibly tight control over thickness variation, defectivity levels had to be significantly reduced.
Though many defectivity issues arose, an insidious one occurred at the wafer bevel due to the redistribution of potentially underexposed gate or overpolished source/drain (S/D) regions. In the optimization of within-wafer uniformity, optimization of the bevel region is critical because it can lead to redistribution of bevel films during subsequent poly etch and wet etch operations. In another case, structural damage due to high CMP shear forces causes low yield and reliability issues or even relaxation of purposely stressed films. Steigerwald said the many defect modes (Table) were addressed primarily through improvements in consumables (pads and slurry) and procedures. For the poly opening polish (POP) step, a high-selectivity slurry provided the best solution.
CMP Defect Modes
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Defect mode |
Potential causes |
Impact to device |
Potential solutions |
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Particles |
Slurry/pad residue Polish byproducts |
Shorting/opens Pattern distortion |
Cleaner tooling Clean chemistries |
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Macro scratches |
Large/hard foreign particles on polish pad |
Pattern removal over multiple die |
Pad conditioning Pad cleaning Environment |
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Micro scratches |
Slurry agglomeration Pad asperities |
Shorting/opens |
Slurry filters Pad/pad conditioning |
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Corrosion (metal CMP) |
Slurry chemistry Clean chemistry |
Opens Reliability |
Passivating films Chemistry optimization |
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Film delamination |
Weak adhesion CMP shear force |
Shorting/opens Device parametrics |
Improve adhesion Low-pressure CMP |
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Oprganic residue |
Inadequate cleaning Residual slurry Components |
Shorting/opens Disturbed patterning of next layer |
Cleaner tooling Slurry optimization Clean chemistries |
For interconnects, copper metal loss during CMP (dishing and erosion effects), is a primary cause of interconnect height variation at the 45 nm node. For metal gates, any variation in height will affect the gate resistance and transistor operation, including threshold voltage shifts. To reduce within-wafer and wafer-to-wafer metal thickness variation, Intel applied similar concepts as at the interconnect levels, including control of pattern density where possible.
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| Top-down and cross-sectional views of etched raised S/D exposed during POP CMP step and subsequently attacked during post-CMP poly removal. |
Stiegerwald concluded with a recommendation that consumable formulations must follow a more condensed timeline for development. He gave the examples that shallow trench isolation (STI) consumables took 10 years to develop and copper CMP consumables took four years. “We need the industry to follow a two-year development timeline,” he said, adding that better process control of materials must take place at the manufacturer so that excursions do not occur in the process line but at the consumable supplier’s facility instead.
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