Hybrid Wafers Boost Performance
Peter Singer, Editor-in-Chief -- Semiconductor International, 12/1/2004
Most wafers today are processed on silicon sliced on the (100) plane and oriented in the &110> direction (as determined by a notch in the wafer). A simple reorientation of device channels to the &100> channel can increase hole mobility in PMOS devices by ~15%, in an effect similar to what is seen in strained silicon devices (see "Strain Equals Gain: The New Face of Silicon "). This is done either by changing the layout of the PMOS transistors during design, or re-orienting channel direction on the standard (100) surface orientation.
Changing the wafer's surface orientation from (100) to (110) can enhance PMOS hole mobility by ~2×. Unfortunately, NMOS electron mobility is also degraded by ~2× with this approach. The solution? Combine both (110) and (100) silicon in a hybrid substrate through the use of cleaving, bonding, etching and selective epitaxy.
Hybrid substrates with different crystal orientations were first proposed by IBM in 2003 at the International Electron Devices Meeting, where a 40-65% performance enhancement was reported for 90 nm CMOS technology. Additional work will be presented at this year's conference (Dec. 12-15 in San Francisco). In separate papers, researchers from Toshiba and the University of Tokyo describe how they used channel orientation designs in conjunction with stress control to optimize mobility for 45 nm devices.
In IBM's hybrid-orientation technology, which provides the convenient acronym "HOT," layer transfer process, block-level trench etch, epitaxial regrowth and CMP were performed before conventional CMOS device processes. First, hydrogen was implanted into an oxidized silicon substrate with (110) orientation (or alternatively another substrate with (100) orientation). Then, the wafer was flip-bonded to a handle wafer with different surface orientation. A two-phase heat treatment was then carried out to split the hydrogen-implanted wafer and strengthen the bonding. Because of the different activation energy, a (110) wafer requires a higher splitting temperature. Finally, the top SOI layer was polished and thinned down to the desired thickness, about 50 nm.
Processing required one additional lithography level to etch through the silicon-on-insulator (SOI) and buried oxide layers to expose the surface of the handle wafer. Following a spacer formation, epitaxial silicon was grown through the opening by RTCVD. As is the nature of epitaxy, the epitaxial silicon will be in the same crystal orientation as the handle wafer. To avoid potential problems from facets caused by the selective epitaxy, the epitaxial silicon was planarized by CMP and etched so that it was level with the SOI surface (Figure ).
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Obviously, there are two choices when it comes to hybrid substrates: whether the handle wafer and the ensuing selective epitaxy is in the (100) or (110) orientation. With the former, it's possible to use mature (100) silicon epitaxy and a lower-temperature cleavage; however, it is necessary to develop (110) layer transfer and wafer-bonding techniques. A (110) substrate, on the other hand, means the NMOS is on SOI and the PMOS is on the (110) epi layer. This has performance advantages, but it requires (110) silicon selective epitaxy, which is more difficult.
In the Toshiba work, the researchers further examined the mobility improvement effect of &100> channel on (100) plane CMOS devices by adding local stress with tensile direction, and have confirmed experimentally and theoretically that drain current of both NMOS and PMOS can be improved by 20% and 10%, respectively. They also claim that their scheme of strategy enhancement technology is highly manufacturable and applicable to the 45 nm node.
The reason why crystal orientation and silicon strain have such a big impact on carrier mobility is rather complicated, having to do with the shape and number of the valence and conduction bands. The University of Tokyo researchers describe it in this way: "The mechanism of mobility enhancement and its strain dependence are well explained by carrier repopulation and energy band structure deformation."
For additional information on emerging technologies, go to www.semiconductor.net/emerging
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