TSMC Sketches 32 nm Rollout Plan for 2009
David Lammers, News Editor -- Semiconductor International, 4/28/2008
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Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC, Hsinchu, Taiwan) plans to roll out its 32 nm process offerings in the third quarter of 2009, with evaluation kits available now for early adopters, said Jack Sun, vice president of R&D.
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| Jack Sun, Vice President of R&D, TSMC |
The first iteration of the 32 nm design kits will become available later this year, but some silicon-proven IP is available now for 32 nm evaluation work, Sun said. TSMC will offer general purpose and low-power 32 nm processes with a conventional oxynitride gate oxide.
Sun Microsystems Inc. (Santa Clara, Calif.) announced in February that it would switch from Texas Instruments Inc. (TI, Dallas) to TSMC as the foundry for its 45 nm and beyond microprocessors, giving TSMC a technology driver at the high end. The high-performance 32 nm technology used for the Sun Microsystems microprocessors will use “our own version of high-k,” Sun said.
| TSMC will push the numerical aperture of immersion scanners for 32 nm processing. |
Also, dual core processors aimed at 3G smart phones are a major target for the 32 nm generation, a market where Sun said “fast and cool” are the bywords driving technology choices. At the International Electron Devices Meeting (IEDM) held in Washington, D.C., last December, TSMC presented its low-power 32 nm technology, with a drive current of 1200/750 µA/µm for the NMOS and PMOS devices at a leakage current of 100 nA/µm.
“The computer CPU guys hit the power wall first a few years ago, but now the graphics and smart phone customers really focus on energy efficiency. The cell phone customers need multiple threshold voltages and double and triple oxide layers,” Sun said.
Some double patterning lithography will be required at 32 nm to avoid corner rounding at the critical layers. Sun said TSMC has invested heavily in a design for manufacturing (DFM) solution that promotes restricted design rules aimed at more regular lithography patterns and avoidance of chemical mechanical polishing (CMP) hot spots.
TSMC has developed proprietary methods to reduce resistance in the copper interconnect, as well as pushing the enhanced low-k to a slightly lower dielectric value at the 32 nm node. He declined to provide details.
| TSMC targets its process platforms at a wide variety of markets. |
Asked if customers were becoming increasingly reluctant to move to the next node, Sun said TSMC is investing more resources in design enablement, including “foundation IP,” which TSMC provides to its customers. “We provide more of the foundation IP so the customers can spend their precious dollars on the IP that they need to port into a new node. Not everybody has the resources to design into this type of process. There is no doubt that economics are pushing on Moore’s Law. Indeed, the lithography tool cost is increasing, but the litho suppliers are working very hard to improve their throughput.”
TSMC is also investigating maskless lithography, although he said, “By and large, the mask cost itself is not a big issue for the people who scale.”
TSMC executives are presenting their technology roadmaps in a series of day-long technology symposiums. The events in San Jose and Boston were held last week, with the North America tour concluding today in Austin, Texas.
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Looking at the roadmap, 45 nm is 1.2 NA, and 32 nm is 1.35 NA, so I simple-mindedly interpret 22 nm to be double patterning 1.2 NA and 15 nm double patterning 1.35 NA.
guest - 5/1/2008 7:47:00 PM CDT -
Optical maskless offers more ways of extending 193 nm immersion than regular masked lithography. A mask can only improve resolution so much, but the fabrication limits the ability to control the diffraction pattern. I think it is worth considering more seriously.
lasik novice - 4/30/2008 7:18:00 AM CDT
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