Dielectric Etch Faces Material, Process Choices

Alexander E. Braun, Senior Editor -- Semiconductor International, 6/1/2004

At a Glance With the move to 193 nm lithography, dielectric etch is going through a major transition point, facing issues induced by a balancing act of organic, inorganic and metal materials, as well as etch selectivity questions. These conditions are exacerbated as the technology migrates toward the 90 nm node, and extreme high aspect ratios complicate etch and photoresist integrity and selectivity. Sidebars: Low-K Damage During Photoresist Strip

A photoresist pattern is formed on a wafer's surface to be transferred to the layer below it through etching. The material is then selectively removed from the substrate or thin films on it. This must be done with utmost precision; however, progressively smaller geometries, exotic materials and larger wafer sizes sometimes make this easier said than done (Fig. 1 ).
 
"Dielectric etch poses different demands for FEOL and BEOL," said Brian Shieh, general manager of the dielectric etch division of Applied Materials (Santa Clara, Calif.). "Each has different requirements, which points to the need for the reactor to have the fundamental flexibility to perform well in a variety of applications."
 
"When dielectric etch is considered," said Michael Mills, director of emerging technology at Dow Chemical (Midland, Mich.), "there probably aren't equipment limitations now or in the near future."

"Currently, the focus is on the approach for dual-damascene-type processes, low-k, and high-aspect-ratio contacts," said Jason Ghormley, senior process manager for Hitachi High Technologies America (Dallas). "From an oxide etch standpoint, the anisotropic profile must be controlled without getting too much sidewall passivation, and balanced with a good overall profile. This is a universal issue with oxide etch because its process control is chemical-dependent. On an oxide platform, it's useful to have silicon sources in the chamber to control the free fluorine to carbon containing radical ratios. This helps balance the amount of active etch being obtained vertically, while controlling the amount of sidewall passivation."

BEOL and FEOL impacts

1. The etching process today must offer solutions that works well regardless of the user’s approach, providing a wide operating window for an optimum processing environment and performance control for next- generation materials and geometries. (Source: Applied Materials)

Applied's Shieh characterized dual-damascene as a complex application, because of the variety of materials and integration schemes used — for example, partial or full via fill with photoresist or BARC, and multilevel masks, whether hard masks or metal masks. "What is needed is a solution that works well regardless of the user's approach," he said. "An answer is a wide operating window that allows an optimum processing environment and performance control for next-generation materials and geometries. Such capability addresses both FEOL and BEOL issues. Small design adjustments may be needed for FEOL vs. BEOL, but the underlying capability is there."

For FEOL, the challenge is smaller and higher-aspect-ratio features in which the focus is on ensuring correct selectivity and controlling the profile and top/bottom CD. "From the hardware perspective, you need high-flow/low-pressure capability for shorter residence times. It is also essential to control ion density and energy distribution in addition to merely decoupling density and average energy," Shieh said. "On the process side, plasma chemistries with the appropriate etch species mix need to be optimized."

The focus on minimizing low-k damage is universal. There is a migration toward lower k values and, at BEOL, integration schemes are devised to provide the lowest obtainable effective capacitance. "The damage — physical and electrical — that low-k sustains during dielectric etch is well known," Shieh said. "By developing features that make possible a wide operating window, an etch reactor can effectively perform an in situ strip in the ultralow-pressure/low-energy regimes that best preserve k values. Its clean mode operation should eliminate the fluorine memory effect. These capabilities further protect k-value integrity and enable multistep processing in one chamber, reducing cycle time."

Selectivity considerations

Dow Chemical's Mills sees dielectric etch hurdles stemming from etch selectivity demands. "The consensus is a 20:1 etch selectivity is required for true manufacturability," he said. Thus, the material being etched must be removed 20× faster than whatever material is being used to pattern or hold the geometry. "Historically, that has been photoresist. When oxide or FSG were etched, you only needed an oxide removal rate 20× faster than photoresist's — not too challenging chemically, since photoresist is wholly organic and oxide or FSG is inorganic. With SiLK, we were asked how to etch it in the beginning because, like photoresist, it's an organic. The technology adopted used a thin inorganic layer, and the pattern was etched from the photoresist into the inorganic layer, which acted like the photoresist to etch the organic SiLK film. Etch selectivities between SiLK and oxide are high — 40:1."

Difficulties arise when materials that are neither organic nor inorganic, but something in between, are included. "Now you need something that etches slowly, compared to hybrid or OSG-like materials," Mills said. "It comes down to three solutions. One is to make a multiple-stack hard mask for etching purposes, which has organic, inorganic, or even metal layers, because a metal is chemically different from organic and inorganic, and it's possible to find a chemistry that will etch it. There are three material classes: organic, inorganic or metal, and it's best to use one of the three rather than a composite or homogeneous mixture.

"The second way is incorporating one, two and three layers of a hard or etch mask on top. The layers are stacked, so that when the different aspects are etched — the trench, the via, etc. — there's always one material exposed, chemically different from the one to be etched." UMC, IBM and others have incorporated a thin metal layer, a titanium- or tantalum-based layer, because at one point of the etch process they lacked the needed chemical selectivity.

The third option is a single-damascene process, proposed by NEC for its 130 and 90 nm nodes. Instead of controlling via height independently from the trench's depth in etching, they build the via and then the trench. This is a costly compromise that meets line uniformity metrics.

Things will be difficult for dielectric materials composed of both organic and inorganic units, such as OSG materials, because an increase in carbon content — which can significantly impact etch selectivity to photoresist — is being proposed to further lower the dielectric constant. Interestingly, the other approach — adding voids or air — improves etch selectivity. If porous oxide is being etched, and photoresist is used to pattern it, and there is an etch rate difference of 20:1 for dense oxide, the porous oxide version will etch up to 2-3× faster. This boosts etch selectivity to 40 or 60. Just making an inorganic or organic base material porous increases the overall etch rate of one material relative to the hard mask used. It is only when the material is varied compositionally, and it begins resembling either photoresist or one of the etch mask materials, that issues arise (Fig. 2 ).

2. The dielectric etch of dual-damascene structures highlights the importance of the etch mask stack configuration. The compositional makeup of the individual layers within the etch mask stack, as well as the sequence of etch (and strip) operations, is being continuously optimized. The function of the etch mask stack is a combination of high etch selectivity(>20:1) during etch of the underlying dual-damascene configuration and etch parity to enable discrete layer removal or simultaneous pattern definition and etch of some underlying structure. (Source: 2003 ITRS)

Another serious issue is etch damage — visually apparent in a SEM or not — done to the remaining material. "The nice thing about dense dielectric oxide, FSG, is that you remove material from a surface, but don't do any damage ahead of that," Mills said. "When you get to more open structures and materials with chemically different layers, an etch chemistry that removes both layers at the same rate is difficult to get. For a hybrid material with organic and inorganic functionality, something is needed to attack the Si- as well as the C-bond, at a rate proportional to their concentration within the ILD material. Unfortunately, it's difficult to get both reactions to occur at the same rate. An issue associated with etch is that you don't know how much damage you've done until the wet clean process or barrier deposition — it's hidden, so when there's a cleaning or barrier issue, it's sometimes traceable back multiple process steps to the etch process."

One can have a superb OSG film etch structure, and after wet clean the CD changes by 50%. The topography that the etch process leaves on a structure's sidewall can be a blessing or a nightmare for the barrier process. If smooth and continuous, without breaks or inverted sidewall slopes, the barrier process has a large process margin or window. This was the case at least through oxide and homogeneous FSG dual-damascene, because of the processes' high etch selectivity. "We're now seeing things called 'veiling,' 'bat wings' and microtrenching on side structures — all things barrier metal and ECD engineers are deathly afraid of," Mills said. "With lower-density structures, there's a fine level of sidewall topography, which offers 1 and 2 and 4 nm types of disparities, which are just as challenging for the barrier."

"Nobody has total solutions — everybody's specializing right along the materials," said John Almerico, director of product marketing at Tegal (Petaluma, Calif.). "High-k is an area where we have technical advantages to build upon our experience in ferroelectric film etching. Passivation pad etch is another specialty of ours — a solid, non-critical dielectric etch, using mature technology, which still does a very cost-effective job. In between, we see increasing use of dielectric materials as hard mask materials. This is a new area that pushes CDs in the use of dielectric films as sacrificial layers."

Etch in transition

With the move to 193 nm lithography, dielectric etch is going through a transition. Jeff Marks, vice president of dielectric etch products at Lam Research Corp. (Fremont, Calif.), sees this occurring at the 90 nm node and in volume production at 130 nm both in logic and memory, pushing 110 nm on the memory side.

The challenges on the front end, particularly with DRAMs, is the increasing aspect ratio of the etch, as for cell capacitor structures. When going from 110 to 90 nm, it becomes difficult to etch that deep (>2.5 µm) and maintain photoresist integrity and selectivity needed for acceptable profile and striation performance. Limits are being pushed and alternatives being sought — such as sacrificial mask schemes — including polysilicon or multilayer resist masks. In the back end, the key challenge is the implementation of various low-k materials. The industry is moving toward carbon-doped oxide films, predominantly OSG films, with some using organic low-k material.

The 193 nm resist is considerably less robust than its 248 nm counterpart, and it must be made thinner. "How do we achieve high selectivity to the photoresist and etch these deep, small features so that the surface is smooth around the hole or along the line, influencing line edge roughness?" Marks asked. "You need to ensure there isn't much wiggle or striations along the lines or the holes. And you need to do this with resist that is much more prone to damage and sensitive to ion bombardment."

Lam has optimized the use of dual-frequency plasma to adjust ion energy and minimize photoresist damage. "We've also looked into gas chemistries and manipulation schemes within the reactor to improve photoresist selectivities," Marks said. "There's a considerable cost savings in avoiding multilayer resist or polysilicon hard masks. We've demonstrated deep etching with thin, 193 nm photoresist, eliminating the need for multilayer masks in some cases." A typical MLR scheme has a thin 193 nm photoresist, an OSG or some other dielectric layer, then a thicker photoresist. The top layer is used as an image to then open the oxide mask and the thick photoresist, and then that is used at the mask for etching.

In the BEOL, in situ processing capability is gaining acceptance as the way to reduce cycle time and inventory costs. "You want to process multiple films in one chamber, without memory effects impacting the next material's etch," Marks said. "Some schemes proposed for 65 or 45 nm require 10 different etch step in 10 different chambers. Confining the plasma minimizes the memory effect, and a dual-frequency configuration provides efficient polymer management to enable in situ processing of some of these films."

When film is etched, a protective barrier layer forms on the low-k material's surface. "You want to keep that barrier and minimize fluorine in the chamber," Marks said. "There are different approaches to in situ processing: You can etch the wafer, attempt to clean residual polymers from the chamber, and go into the main strip process. However, when you remove the chamber polymer while the wafer is still inside the chamber, you eliminate the wafer's protective layer. The optimal solution is to minimize polymer deposition inside the chamber, so that when you go into the oxygen plasma, or hydrogen plasma strip, you strip as you remove the protective layer, keeping it as long as possible, minimizing damage."

Maintaining dimension control in production is also becoming a challenge. What was once a challenge for silicon gate etch is appearing in the dielectric arena. "In the back end, for dual-damascene structures, CD line control is carefully monitored. In the front end, CD line control is needed for gate masks. Many device manufacturers still use a dielectric etcher to pattern the gate mask, and control must be tight. If you look at how densely spaced the holes are getting on some of the contact etches, it is clear that you must have tight CD control; otherwise, bridging and other problems result."

At 90 and 65 nm, control and variation requirements are to within a few nanometers' difference. "You need &5 nm CD repeatability across the wafer, wafer-to-wafer and chamber-to-chamber," Marks said. "Very repeatable results are necessary, which can only be achieved by being able to tune the process to adjust the CD across the wafer. Sometimes, incoming lithography isn't good across the wafer; ideally, one could compensate for this in the etch process."

3. Some 130 nm low-k vias, showing good CD and profile control, etched on a 300 mm TEL dielectric etcher. (Source: International SEMATECH)

"The buck stops at etch," said Eric Lee, BEOL integration product marketing manager for Tokyo Electron Ltd. (TEL, Austin, Texas). "Even with lithography's rework processes, if anything deficient in the features' shapes comes out of lithography, etch must provide solutions to get to the ultimate design parameter envisioned. Substantial R&D will be needed, particularly if immersion systems are adopted for pattern generation." Lee views high-density plasma as pretty much dead for back-end etch, with nearly all manufacturers considering some type of medium-density plasma tool. "Almost everyone is experimenting with combinations of at least two power sources and low-electron-temperature chemistries to get a reduced plasma damage signature at the transistor level," he said (Fig. 3 ).

The metrology challenge

Michael Gostein, chief technologist at Philips AMS (Natick, Mass.), believes major etch metrology challenges come from a combination of decreasing linewidths and increasing aspect ratios. "People want to control parameters such as line profile, but even basics such as linewidth and depth are becoming more difficult using existing techniques. CD-SEM, optical metrology and AFM all face difficulties at future nodes and require development. We're interested in the problem of measuring the depth of very high-aspect-ratio structures (e.g., >10) with narrow linewidth. An alternative technique — possibly acoustics — would get the industry's attention."

Jon Opsal, CTO of Therma-Wave (Fremont, Calif.), views footing and undercut occurring during dielectric etch as an area of concern in fabs. "Process engineers want to know, 'Did I etch enough?' or 'Did I encroach on something I wasn't supposed to?' The undercut problem will be one of the major issues for many engineers, and they will want to be able to measure it."

In measuring structures after etch, the challenge is not just measuring thickness, but also shape, linewidth and sidewall angle. "Increasingly, we're challenged to do this within continuing tightening specifications for metrology," Opsal said. "For example, at the 90 nm node, we're already confronted with actual structures on the scale of 60 to 70 nm. At 65 nm, it'll be for 40 nm structures, and at the 32 nm node we'll have to look at 20 nm structures, which we're already measuring with sub-nanometer precision."