Front-End Advances Strengthen Performance

Peter Singer, Editor-in-Chief -- Semiconductor International, 6/15/2006

The semiconductor industry has continued its push to ever-smaller dimensions, moving to a new technology generation every two to three years. Leading-edge volume production is now moving from 90 to 65 nm, and R&D work is focused on next-generation 45 and 32 nm. The International Technology Roadmap for Semiconductors (ITRS) has these generations slated to move into production in 2009 and 2011, respectively, although Intel has already demonstrated working 45 nm chips earlier this year, with a stated production goal of 2007 on 300 mm wafers (Fig. 1 ).

Semiconductor processing is often separated into "front end" and "back end" steps, with front end referring to the fabrication of the transistors, and back end referring to the on-chip "wiring" or interconnects. For the 45 and 32 nm generations, much of the industry's focus will be on the front end, since that is where the biggest gains in performance are expected. The two biggest goals are to reduce leakage current and increase speed. Leakage current is particularly important for low-power chips used in mobile applications, since excessive leakage current both consumes power and increases heat.

There has been great interest in three-dimensional transistor structures, most notably the finFET. The advantage of this type of a device is that the gate of the transistor is wrapped around the channel region, enabling more effective control of drive and leakage current (i.e., the current when the device is on and off). Although there has been significant progress in understanding the many manufacturing challenges associated with putting such devices in production (mostly lithography and cleaning challenges), it does not look like 3-D structures will come into play for the 45 nm generation. Instead, the focus will be on strained silicon, which can boost overall chip speed by a whopping 40% compared with non-stressed devices.

1. Intel plans to start fabricating devices with 45 nm technology on 300 mm wafers starting in 2007. A wafer with SRAM test chips is shown. (Source: Intel)

As shown in Figure 2 , strain engineering involves straining of the silicon crystal to increase the mobility of charge carriers in the channel (electrons in NMOSFETs and holes in PMOSFETs). An added benefit is that it reduces the source/drain series resistance. Compressive strain is induced in PMOS transistors, typically using epitaxially grown SiGe source/drain and/or a compressively strained nitride layer over the gate. The greatest emphasis is given to the PMOSFET, since hole mobility is typically three orders of magnitude less than electron mobility. In NMOS transistors, a tensile-strained nitride layer is used. These processes induce approaches that have proven to be the most manufacturable and cost-effective, and were first implemented in manufacturing at the 90 nm node. Another method that can be used is biaxial strain or global strain, where the entire wafer is strained by various methods. This approach is not likely to enter manufacturing until the 32 nm node or later because of defectivity and integration issues. However, it is expected to complement process-induced (primarily uniaxial) approaches at some point.¹ Beyond the use of strain, there is a focus on new materials for the gate stack. Traditionally, the gate is made up of a heavily doped polysilicon electrode, separated from the channel region by a very thin dielectric, typically SiO₂ or more recently, SiON. The thinness of this dielectric is important in that a thinner dielectric allows for more coupling of the charge from the gate into the channel, which increases drive current and switching speed. If it is too thin, however, excessively high leakage current can result to the point where the off current is almost as high as the on current. A possible solution lies in higher-k dielectrics, most notably hafnium-based silicates. The higher k value enables more charge to be coupled through a thicker material. The problem is one of integration: Higher-k materials have shown to have adhesion problems and also some potential electrical problems related to Fermi pinning, which can cause a shift in threshold voltage (which determines when a transistor turns on and off).

2. Four stress techniques — dual stress liners, stress memorization (SM) and an embedded SiGe source/drain — were fully integrated on a partially depleted SOI substrate. (Source: IBM and AMD)

Initially, it was thought that the push to high-k dielectrics would bring with it a requirement for a move from polysilicon to metal gates. But now metal gates have emerged as a major performance-enhancer, even without high-k. Full silicidation of polysilicon gates (FUSI), particularly using nickel, has become an attractive approach to integrating metallic gates into CMOS devices for low-power applications. Advantages include the compatibility with mainstream polysilicon front-end processing, nickel silicide's mid-gap work function, and the possibility of work function tuning by ion implantation. In addition, since the silicidation takes place at a relatively low temperature, it can be performed after junction activation. However, some of the challenges with FUSI processing include gaining full silicidation on all features and integrating FUSI with minimal impact to the CMOS process. But perhaps the greatest concern is scalability. If companies are going to make a high-k/metal gate change in manufacturing, perhaps a single change to high-k and dual-function metal gates is preferable to an intermediate change to oxynitride/FUSI (a single-generation solution) or high-k/FUSI, only to eventually change to high-k/metal gates.¹

Find more information on front-end processes.

Front-End Process Executive Viewpoints

Mark Namaroff, Senior Vice President of Marketing, Axcelis Technologies

It's no secret that manufacturing cost pressures remain at an all-time high; now more than ever, chip manufacturers struggle to keep new technology adoption in balance with real-world return-on-investment questions. It's a perennial problem, but the good news is that we're beginning to see process developments for the 65 and 45 nm nodes that not only deliver better device speeds and performance, but also offer advantages that help minimize these cost challenges.

One example can be found in the highly cost-sensitive memory device arena, where DRAM manufacturers are moving to dual polygate structures in order to improve device speed. Recent developments in the use of molecular implants, specifically in the use of ClusterBoron, promise dramatic benefits in improving low-energy implant productivity and reducing manufacturing costs. Moreover, this approach has shown specific advantages in enabling effective photoresist removal where other dual polygate applications, such as plasma immersion, lack sufficient cleaning solutions. In other areas, namely for source/drain extensions, molecular implants promise to simplify and eliminate process steps, such as pre-amorphizing implants, and allow manufacturers to use standard anneal technologies rather than having to adopt alternative methods, such as laser or flash annealing.

Moving forward, we expect to see additional advances in ion implantation, such as the continued use of hydrogen implants for silicon on insulator applications, carbon implants for enhancing transistor performance, and many others. We see these developments as the beginning of a new era in ion implantation, where emerging technology needs are met with simple, elegant solutions that promise the productivity and cost benefits necessary for long-term success.

Bob Havemann Vice President of Technology, Process Integration & Applications, Novellus Systems Inc.

Increased density and performance continue to be the key technology drivers for the semiconductor industry. However, growing cost pressures mean device manufacturers must look for new and innovative manufacturing solutions to realize aggressive density and performance goals at affordable cost.

For high-density memory devices, cost and manufacturability issues in the interconnect arena have collided to create an inflection point for conversion from aluminum to copper wiring, and this trend will accelerate as performance factors also come into play. Key factors driving this conversion to copper are the higher cost of scaling aluminum plug fill technology and high defect levels associated with the subtractive aluminum etch process. Another reason for this migration toward copper is because it's a better conductor than aluminum — an attribute that has enabled some companies to decrease the number of layers in their design for additional cost savings.

While density is also important for logic devices and will continue to drive improvements in dielectric and metal deposition technologies, performance is the ultimate measure of product value. The transistor scaling that has heretofore provided the "engine" for significant performance gain at each successive technology generation is running out of steam. Innovative strain engineering techniques such as SiGe and high-stress nitride overlayers have been introduced to "turbo charge" the transistor through mobility enhancement, and these techniques will continue to play an important role in device scaling. Likewise, for the transistor wiring, copper combined with lower-k dielectric insulators will continue to be required to fully leverage circuit performance gains. The need for additional levels of copper interconnect at each generation to co-optimize density and performance will also persist.

Overarching the technology trends that will be presented at this year's SEMICON West is the continuing emphasis on productivity and technology extendibility, as the industry continues to develop innovative solutions for an increasingly cost-sensitive consumer-driven end market.

Arthur H. del Prado, CEO & President, ASM International NV

One of the major challenges semiconductor device makers are facing today is power consumption, particularly in handheld devices and their so-called standby power mode, which causes batteries to leak current when the device is not in use. One of the most promising solutions for addressing standby power consumption is atomic layer deposition (ALD). This technology is winning more supporters as IC makers seek multi-generational solutions to optimum power usage.

ALD creates ultrathin films of exceptional quality and flatness. In the past few years, this technology has come of age, and it is now ready for implementation in the high-volume manufacturing of gate stacks that reduce standby power. Plasma-enhanced chemical vapor deposition (PECVD) is a process that replaces thermal with plasma energy to create more reactive species in the deposition reaction, so the placement of atoms on the wafer is faster. It also allows for greater versatility in selecting precursor molecules.

Manufacturers of DRAMs and RF devices, which both require capacitors with high density and low-leakage current, have all demonstrated the benefits of PECVD. For capacitor applications, the ion bombardment from the plasma can be used to increase the density and, with that, the electrical quality of the oxide layers. Together with the metal electrode layers for top and bottom contacts, unparalleled electrical properties have been demonstrated. In comparative tests, plasma ALD scores 1-2 orders of magnitude lower in leakage current than ALD.

What remains in ALD's development is to find a suitable integration path, and some of the top semiconductor manufacturers are indeed quite close, systematically removing implementation hurdles. Industry-wide adoption of enabling technologies like ALD will offer many benefits throughout our industry and beyond, as they offer a range of applications limited only by our imaginations.

André-Jacques Auberton-Hervé, CEO, Soitec

Two of the hottest topics at SEMICON West 2006 are bound to be power and design. Last year, the buzz was about the new metric: performance per watt. This year, tackling the power challenge has moved into high gear. One of the primary tools is design, and in this age of nanotechnology, design starts at the substrate level.

As SEMICON West approaches, chipmakers on the leading edge of the microprocessor world are focused on their design choices for the 45 nm node. At the heart of these designs are new and evolving ranges of engineered substrate solutions, including SOI, strained SOI and ultrathin SOI. Design innovations like embedded memory technologies leverage SOI for major die-area reductions. High-impedance engineered substrates for RF SoCs are now ready for upcoming device generations. Consistent with these trends, the overall engineered substrate market is in a very high-growth mode.

With the shift in drivers to consumer markets, however, the entire industry has to look at the big picture as never before. When we look at speed, we have to look at heat. When we look at performance, we have to look at power. When we look at manufacturing, we have to look at design. When we look at cost, we have to look up and down the line for the real impact. The fact is, when we look at the direction our industry is taking, we have to look at the entire R&D manufacturing commercial ecosystem. Fortunately, from the engineered substrates vantage point, the view is excellent.

Michael Polcari, President & CEO, Sematech

Long a fixture in executives' travel schedules, SEMICON West has emerged as one of the world's most educational and eclectic displays of cutting-edge microchip technology. From our perspective, the 2006 show — with its first-time

TechXPOTs focused on specific technology and manufacturing areas — will provide some of the best views yet. Here are some examples:

• Advances in lithography for the 45 and 32 nm technology generations, including defect detection and cleaning techniques for EUV mask blanks, and high-NA lens materials and high-refraction fluids for 193 nm immersion.

• Innovations in interconnect, such as development of CVD-based films with low-k effective, and explorations of 3-D modeling and other heterogeneous solutions.

• Breakthroughs in transistor scaling efforts, among them new materials for metal electrodes, MOSFET channels and multi-gate structures.

• Innovations in manufacturing effectiveness, including manufacturability assessments, fab and equipment productivity improvements, and advances in AEC/APC and e-manufacturing technologies.

• A first look at the 2006 update of the International Technology Roadmap for Semiconductors (ITRS), which will identify the barriers and opportunities affecting the above-mentioned technologies.

Most importantly, SEMICON West 2006 stands with other industry meetings in gauging and depicting our collective progress, and reminds us of the overriding importance of collaboration as an affordable means of clearing the R&D and manufacturing hurdles in our critical path. Working together to extend our current technology, build infrastructure for emerging technologies, and perform early exploration of the most promising alternatives is key to our industry's ability to generate the annual innovations that make SEMICON West one of the world's most fascinating expositions.

Craig Kerkove, Vice President & General Manager, Hitachi High Technologies America

With the semiconductor industry's push for ever-smaller geometries and continued advances in speed and power, equipment suppliers are forced to develop new or improved processes that enable their IDM or foundry customers to meet these evolving manufacturing requirements.

The numerous process and production challenges faced by the industry today force equipment suppliers to be experts not only in their own process technology, but also in such areas as materials science, IC design and process integration. For our company, the challenges extend into various IC categories. In logic, the push toward dual metal gate structures and integration schemes for 45 and 32 nm technologies requires the development of new materials, processes and process control techniques. Next-generation flash memory is creating a need for in situ high-k gate etch, with a focus on developing processes for a wide variety of high-k material options. DRAM manufacturers continue to push HARC etch to the extremes with even higher aspect ratio requirements. Finally, while these FEOL changes are occurring rapidly, BEOL interconnect levels are shifting to softer low-k and ultralow-k dielectrics, meaning additional development on the part of the equipment supplier.

This year, etch issues resulting from the industry's transition to 193 nm immersion lithography is one of the biggest challenges. Thinner resists can negatively impact CD uniformity and LWR/LER, and new resist profile problems are beginning to appear. This means that more selective etch processes and chemistries must be developed to cope with thinner resists.

The good news for the equipment industry is that we're seeing strong equipment sales growth this year and likely going into 2007, which will enable us to invest in continued product and process innovation to support our customers. Looking at the big picture, the industry is also increasingly recognizing its responsibility as a good corporate citizen, and is adopting initiatives to reduce energy consumption.

Moving forward, there are major issues surfacing around the adoption of 300 mm Prime and the need to start 450 mm programs — both of which will be costly and require cooperation and collaboration between IDMs and their suppliers.

Front-End Process Executive Viewpoints

Mark Namaroff, Senior Vice President of Marketing, Axcelis Technologies

It's no secret that manufacturing cost pressures remain at an all-time high; now more than ever, chip manufacturers struggle to keep new technology adoption in balance with real-world return-on-investment questions. It's a perennial problem, but the good news is that we're beginning to see process developments for the 65 and 45 nm nodes that not only deliver better device speeds and performance, but also offer advantages that help minimize these cost challenges.

One example can be found in the highly cost-sensitive memory device arena, where DRAM manufacturers are moving to dual polygate structures in order to improve device speed. Recent developments in the use of molecular implants, specifically in the use of ClusterBoron, promise dramatic benefits in improving low-energy implant productivity and reducing manufacturing costs. Moreover, this approach has shown specific advantages in enabling effective photoresist removal where other dual polygate applications, such as plasma immersion, lack sufficient cleaning solutions. In other areas, namely for source/drain extensions, molecular implants promise to simplify and eliminate process steps, such as pre-amorphizing implants, and allow manufacturers to use standard anneal technologies rather than having to adopt alternative methods, such as laser or flash annealing.

Moving forward, we expect to see additional advances in ion implantation, such as the continued use of hydrogen implants for silicon on insulator applications, carbon implants for enhancing transistor performance, and many others. We see these developments as the beginning of a new era in ion implantation, where emerging technology needs are met with simple, elegant solutions that promise the productivity and cost benefits necessary for long-term success.

Bob Havemann Vice President of Technology, Process Integration & Applications, Novellus Systems Inc.

Increased density and performance continue to be the key technology drivers for the semiconductor industry. However, growing cost pressures mean device manufacturers must look for new and innovative manufacturing solutions to realize aggressive density and performance goals at affordable cost.

For high-density memory devices, cost and manufacturability issues in the interconnect arena have collided to create an inflection point for conversion from aluminum to copper wiring, and this trend will accelerate as performance factors also come into play. Key factors driving this conversion to copper are the higher cost of scaling aluminum plug fill technology and high defect levels associated with the subtractive aluminum etch process. Another reason for this migration toward copper is because it's a better conductor than aluminum — an attribute that has enabled some companies to decrease the number of layers in their design for additional cost savings.

While density is also important for logic devices and will continue to drive improvements in dielectric and metal deposition technologies, performance is the ultimate measure of product value. The transistor scaling that has heretofore provided the "engine" for significant performance gain at each successive technology generation is running out of steam. Innovative strain engineering techniques such as SiGe and high-stress nitride overlayers have been introduced to "turbo charge" the transistor through mobility enhancement, and these techniques will continue to play an important role in device scaling. Likewise, for the transistor wiring, copper combined with lower-k dielectric insulators will continue to be required to fully leverage circuit performance gains. The need for additional levels of copper interconnect at each generation to co-optimize density and performance will also persist.

Overarching the technology trends that will be presented at this year's SEMICON West is the continuing emphasis on productivity and technology extendibility, as the industry continues to develop innovative solutions for an increasingly cost-sensitive consumer-driven end market.

Arthur H. del Prado, CEO & President, ASM International NV

One of the major challenges semiconductor device makers are facing today is power consumption, particularly in handheld devices and their so-called standby power mode, which causes batteries to leak current when the device is not in use. One of the most promising solutions for addressing standby power consumption is atomic layer deposition (ALD). This technology is winning more supporters as IC makers seek multi-generational solutions to optimum power usage.

ALD creates ultrathin films of exceptional quality and flatness. In the past few years, this technology has come of age, and it is now ready for implementation in the high-volume manufacturing of gate stacks that reduce standby power. Plasma-enhanced chemical vapor deposition (PECVD) is a process that replaces thermal with plasma energy to create more reactive species in the deposition reaction, so the placement of atoms on the wafer is faster. It also allows for greater versatility in selecting precursor molecules.

Manufacturers of DRAMs and RF devices, which both require capacitors with high density and low-leakage current, have all demonstrated the benefits of PECVD. For capacitor applications, the ion bombardment from the plasma can be used to increase the density and, with that, the electrical quality of the oxide layers. Together with the metal electrode layers for top and bottom contacts, unparalleled electrical properties have been demonstrated. In comparative tests, plasma ALD scores 1-2 orders of magnitude lower in leakage current than ALD.

What remains in ALD's development is to find a suitable integration path, and some of the top semiconductor manufacturers are indeed quite close, systematically removing implementation hurdles. Industry-wide adoption of enabling technologies like ALD will offer many benefits throughout our industry and beyond, as they offer a range of applications limited only by our imaginations.

André-Jacques Auberton-Hervé, CEO, Soitec

Two of the hottest topics at SEMICON West 2006 are bound to be power and design. Last year, the buzz was about the new metric: performance per watt. This year, tackling the power challenge has moved into high gear. One of the primary tools is design, and in this age of nanotechnology, design starts at the substrate level.

As SEMICON West approaches, chipmakers on the leading edge of the microprocessor world are focused on their design choices for the 45 nm node. At the heart of these designs are new and evolving ranges of engineered substrate solutions, including SOI, strained SOI and ultrathin SOI. Design innovations like embedded memory technologies leverage SOI for major die-area reductions. High-impedance engineered substrates for RF SoCs are now ready for upcoming device generations. Consistent with these trends, the overall engineered substrate market is in a very high-growth mode.

With the shift in drivers to consumer markets, however, the entire industry has to look at the big picture as never before. When we look at speed, we have to look at heat. When we look at performance, we have to look at power. When we look at manufacturing, we have to look at design. When we look at cost, we have to look up and down the line for the real impact. The fact is, when we look at the direction our industry is taking, we have to look at the entire R&D manufacturing commercial ecosystem. Fortunately, from the engineered substrates vantage point, the view is excellent.

Michael Polcari, President & CEO, Sematech

Long a fixture in executives' travel schedules, SEMICON West has emerged as one of the world's most educational and eclectic displays of cutting-edge microchip technology. From our perspective, the 2006 show — with its first-time

TechXPOTs focused on specific technology and manufacturing areas — will provide some of the best views yet. Here are some examples:

• Advances in lithography for the 45 and 32 nm technology generations, including defect detection and cleaning techniques for EUV mask blanks, and high-NA lens materials and high-refraction fluids for 193 nm immersion.

• Innovations in interconnect, such as development of CVD-based films with low-k effective, and explorations of 3-D modeling and other heterogeneous solutions.

• Breakthroughs in transistor scaling efforts, among them new materials for metal electrodes, MOSFET channels and multi-gate structures.

• Innovations in manufacturing effectiveness, including manufacturability assessments, fab and equipment productivity improvements, and advances in AEC/APC and e-manufacturing technologies.

• A first look at the 2006 update of the International Technology Roadmap for Semiconductors (ITRS), which will identify the barriers and opportunities affecting the above-mentioned technologies.

Most importantly, SEMICON West 2006 stands with other industry meetings in gauging and depicting our collective progress, and reminds us of the overriding importance of collaboration as an affordable means of clearing the R&D and manufacturing hurdles in our critical path. Working together to extend our current technology, build infrastructure for emerging technologies, and perform early exploration of the most promising alternatives is key to our industry's ability to generate the annual innovations that make SEMICON West one of the world's most fascinating expositions.

Craig Kerkove, Vice President & General Manager, Hitachi High Technologies America

With the semiconductor industry's push for ever-smaller geometries and continued advances in speed and power, equipment suppliers are forced to develop new or improved processes that enable their IDM or foundry customers to meet these evolving manufacturing requirements.

The numerous process and production challenges faced by the industry today force equipment suppliers to be experts not only in their own process technology, but also in such areas as materials science, IC design and process integration. For our company, the challenges extend into various IC categories. In logic, the push toward dual metal gate structures and integration schemes for 45 and 32 nm technologies requires the development of new materials, processes and process control techniques. Next-generation flash memory is creating a need for in situ high-k gate etch, with a focus on developing processes for a wide variety of high-k material options. DRAM manufacturers continue to push HARC etch to the extremes with even higher aspect ratio requirements. Finally, while these FEOL changes are occurring rapidly, BEOL interconnect levels are shifting to softer low-k and ultralow-k dielectrics, meaning additional development on the part of the equipment supplier.

This year, etch issues resulting from the industry's transition to 193 nm immersion lithography is one of the biggest challenges. Thinner resists can negatively impact CD uniformity and LWR/LER, and new resist profile problems are beginning to appear. This means that more selective etch processes and chemistries must be developed to cope with thinner resists.

The good news for the equipment industry is that we're seeing strong equipment sales growth this year and likely going into 2007, which will enable us to invest in continued product and process innovation to support our customers. Looking at the big picture, the industry is also increasingly recognizing its responsibility as a good corporate citizen, and is adopting initiatives to reduce energy consumption.

Moving forward, there are major issues surfacing around the adoption of 300 mm Prime and the need to start 450 mm programs — both of which will be costly and require cooperation and collaboration between IDMs and their suppliers.

Front-End Process Executive Viewpoints

Mark Namaroff, Senior Vice President of Marketing, Axcelis Technologies

It's no secret that manufacturing cost pressures remain at an all-time high; now more than ever, chip manufacturers struggle to keep new technology adoption in balance with real-world return-on-investment questions. It's a perennial problem, but the good news is that we're beginning to see process developments for the 65 and 45 nm nodes that not only deliver better device speeds and performance, but also offer advantages that help minimize these cost challenges.

One example can be found in the highly cost-sensitive memory device arena, where DRAM manufacturers are moving to dual polygate structures in order to improve device speed. Recent developments in the use of molecular implants, specifically in the use of ClusterBoron, promise dramatic benefits in improving low-energy implant productivity and reducing manufacturing costs. Moreover, this approach has shown specific advantages in enabling effective photoresist removal where other dual polygate applications, such as plasma immersion, lack sufficient cleaning solutions. In other areas, namely for source/drain extensions, molecular implants promise to simplify and eliminate process steps, such as pre-amorphizing implants, and allow manufacturers to use standard anneal technologies rather than having to adopt alternative methods, such as laser or flash annealing.

Moving forward, we expect to see additional advances in ion implantation, such as the continued use of hydrogen implants for silicon on insulator applications, carbon implants for enhancing transistor performance, and many others. We see these developments as the beginning of a new era in ion implantation, where emerging technology needs are met with simple, elegant solutions that promise the productivity and cost benefits necessary for long-term success.

Bob Havemann Vice President of Technology, Process Integration & Applications, Novellus Systems Inc.

Increased density and performance continue to be the key technology drivers for the semiconductor industry. However, growing cost pressures mean device manufacturers must look for new and innovative manufacturing solutions to realize aggressive density and performance goals at affordable cost.

For high-density memory devices, cost and manufacturability issues in the interconnect arena have collided to create an inflection point for conversion from aluminum to copper wiring, and this trend will accelerate as performance factors also come into play. Key factors driving this conversion to copper are the higher cost of scaling aluminum plug fill technology and high defect levels associated with the subtractive aluminum etch process. Another reason for this migration toward copper is because it's a better conductor than aluminum — an attribute that has enabled some companies to decrease the number of layers in their design for additional cost savings.

While density is also important for logic devices and will continue to drive improvements in dielectric and metal deposition technologies, performance is the ultimate measure of product value. The transistor scaling that has heretofore provided the "engine" for significant performance gain at each successive technology generation is running out of steam. Innovative strain engineering techniques such as SiGe and high-stress nitride overlayers have been introduced to "turbo charge" the transistor through mobility enhancement, and these techniques will continue to play an important role in device scaling. Likewise, for the transistor wiring, copper combined with lower-k dielectric insulators will continue to be required to fully leverage circuit performance gains. The need for additional levels of copper interconnect at each generation to co-optimize density and performance will also persist.

Overarching the technology trends that will be presented at this year's SEMICON West is the continuing emphasis on productivity and technology extendibility, as the industry continues to develop innovative solutions for an increasingly cost-sensitive consumer-driven end market.

Arthur H. del Prado, CEO & President, ASM International NV

One of the major challenges semiconductor device makers are facing today is power consumption, particularly in handheld devices and their so-called standby power mode, which causes batteries to leak current when the device is not in use. One of the most promising solutions for addressing standby power consumption is atomic layer deposition (ALD). This technology is winning more supporters as IC makers seek multi-generational solutions to optimum power usage.

ALD creates ultrathin films of exceptional quality and flatness. In the past few years, this technology has come of age, and it is now ready for implementation in the high-volume manufacturing of gate stacks that reduce standby power. Plasma-enhanced chemical vapor deposition (PECVD) is a process that replaces thermal with plasma energy to create more reactive species in the deposition reaction, so the placement of atoms on the wafer is faster. It also allows for greater versatility in selecting precursor molecules.

Manufacturers of DRAMs and RF devices, which both require capacitors with high density and low-leakage current, have all demonstrated the benefits of PECVD. For capacitor applications, the ion bombardment from the plasma can be used to increase the density and, with that, the electrical quality of the oxide layers. Together with the metal electrode layers for top and bottom contacts, unparalleled electrical properties have been demonstrated. In comparative tests, plasma ALD scores 1-2 orders of magnitude lower in leakage current than ALD.

What remains in ALD's development is to find a suitable integration path, and some of the top semiconductor manufacturers are indeed quite close, systematically removing implementation hurdles. Industry-wide adoption of enabling technologies like ALD will offer many benefits throughout our industry and beyond, as they offer a range of applications limited only by our imaginations.

André-Jacques Auberton-Hervé, CEO, Soitec

Two of the hottest topics at SEMICON West 2006 are bound to be power and design. Last year, the buzz was about the new metric: performance per watt. This year, tackling the power challenge has moved into high gear. One of the primary tools is design, and in this age of nanotechnology, design starts at the substrate level.

As SEMICON West approaches, chipmakers on the leading edge of the microprocessor world are focused on their design choices for the 45 nm node. At the heart of these designs are new and evolving ranges of engineered substrate solutions, including SOI, strained SOI and ultrathin SOI. Design innovations like embedded memory technologies leverage SOI for major die-area reductions. High-impedance engineered substrates for RF SoCs are now ready for upcoming device generations. Consistent with these trends, the overall engineered substrate market is in a very high-growth mode.

With the shift in drivers to consumer markets, however, the entire industry has to look at the big picture as never before. When we look at speed, we have to look at heat. When we look at performance, we have to look at power. When we look at manufacturing, we have to look at design. When we look at cost, we have to look up and down the line for the real impact. The fact is, when we look at the direction our industry is taking, we have to look at the entire R&D manufacturing commercial ecosystem. Fortunately, from the engineered substrates vantage point, the view is excellent.

Michael Polcari, President & CEO, Sematech

Long a fixture in executives' travel schedules, SEMICON West has emerged as one of the world's most educational and eclectic displays of cutting-edge microchip technology. From our perspective, the 2006 show — with its first-time

TechXPOTs focused on specific technology and manufacturing areas — will provide some of the best views yet. Here are some examples:

• Advances in lithography for the 45 and 32 nm technology generations, including defect detection and cleaning techniques for EUV mask blanks, and high-NA lens materials and high-refraction fluids for 193 nm immersion.

• Innovations in interconnect, such as development of CVD-based films with low-k effective, and explorations of 3-D modeling and other heterogeneous solutions.

• Breakthroughs in transistor scaling efforts, among them new materials for metal electrodes, MOSFET channels and multi-gate structures.

• Innovations in manufacturing effectiveness, including manufacturability assessments, fab and equipment productivity improvements, and advances in AEC/APC and e-manufacturing technologies.

• A first look at the 2006 update of the International Technology Roadmap for Semiconductors (ITRS), which will identify the barriers and opportunities affecting the above-mentioned technologies.

Most importantly, SEMICON West 2006 stands with other industry meetings in gauging and depicting our collective progress, and reminds us of the overriding importance of collaboration as an affordable means of clearing the R&D and manufacturing hurdles in our critical path. Working together to extend our current technology, build infrastructure for emerging technologies, and perform early exploration of the most promising alternatives is key to our industry's ability to generate the annual innovations that make SEMICON West one of the world's most fascinating expositions.

Craig Kerkove, Vice President & General Manager, Hitachi High Technologies America

With the semiconductor industry's push for ever-smaller geometries and continued advances in speed and power, equipment suppliers are forced to develop new or improved processes that enable their IDM or foundry customers to meet these evolving manufacturing requirements.

The numerous process and production challenges faced by the industry today force equipment suppliers to be experts not only in their own process technology, but also in such areas as materials science, IC design and process integration. For our company, the challenges extend into various IC categories. In logic, the push toward dual metal gate structures and integration schemes for 45 and 32 nm technologies requires the development of new materials, processes and process control techniques. Next-generation flash memory is creating a need for in situ high-k gate etch, with a focus on developing processes for a wide variety of high-k material options. DRAM manufacturers continue to push HARC etch to the extremes with even higher aspect ratio requirements. Finally, while these FEOL changes are occurring rapidly, BEOL interconnect levels are shifting to softer low-k and ultralow-k dielectrics, meaning additional development on the part of the equipment supplier.

This year, etch issues resulting from the industry's transition to 193 nm immersion lithography is one of the biggest challenges. Thinner resists can negatively impact CD uniformity and LWR/LER, and new resist profile problems are beginning to appear. This means that more selective etch processes and chemistries must be developed to cope with thinner resists.

The good news for the equipment industry is that we're seeing strong equipment sales growth this year and likely going into 2007, which will enable us to invest in continued product and process innovation to support our customers. Looking at the big picture, the industry is also increasingly recognizing its responsibility as a good corporate citizen, and is adopting initiatives to reduce energy consumption.

Moving forward, there are major issues surfacing around the adoption of 300 mm Prime and the need to start 450 mm programs — both of which will be costly and require cooperation and collaboration between IDMs and their suppliers.

Front-End Process Executive Viewpoints

Mark Namaroff, Senior Vice President of Marketing, Axcelis Technologies

It's no secret that manufacturing cost pressures remain at an all-time high; now more than ever, chip manufacturers struggle to keep new technology adoption in balance with real-world return-on-investment questions. It's a perennial problem, but the good news is that we're beginning to see process developments for the 65 and 45 nm nodes that not only deliver better device speeds and performance, but also offer advantages that help minimize these cost challenges.

One example can be found in the highly cost-sensitive memory device arena, where DRAM manufacturers are moving to dual polygate structures in order to improve device speed. Recent developments in the use of molecular implants, specifically in the use of ClusterBoron, promise dramatic benefits in improving low-energy implant productivity and reducing manufacturing costs. Moreover, this approach has shown specific advantages in enabling effective photoresist removal where other dual polygate applications, such as plasma immersion, lack sufficient cleaning solutions. In other areas, namely for source/drain extensions, molecular implants promise to simplify and eliminate process steps, such as pre-amorphizing implants, and allow manufacturers to use standard anneal technologies rather than having to adopt alternative methods, such as laser or flash annealing.

Moving forward, we expect to see additional advances in ion implantation, such as the continued use of hydrogen implants for silicon on insulator applications, carbon implants for enhancing transistor performance, and many others. We see these developments as the beginning of a new era in ion implantation, where emerging technology needs are met with simple, elegant solutions that promise the productivity and cost benefits necessary for long-term success.

Bob Havemann Vice President of Technology, Process Integration & Applications, Novellus Systems Inc.

Increased density and performance continue to be the key technology drivers for the semiconductor industry. However, growing cost pressures mean device manufacturers must look for new and innovative manufacturing solutions to realize aggressive density and performance goals at affordable cost.

For high-density memory devices, cost and manufacturability issues in the interconnect arena have collided to create an inflection point for conversion from aluminum to copper wiring, and this trend will accelerate as performance factors also come into play. Key factors driving this conversion to copper are the higher cost of scaling aluminum plug fill technology and high defect levels associated with the subtractive aluminum etch process. Another reason for this migration toward copper is because it's a better conductor than aluminum — an attribute that has enabled some companies to decrease the number of layers in their design for additional cost savings.

While density is also important for logic devices and will continue to drive improvements in dielectric and metal deposition technologies, performance is the ultimate measure of product value. The transistor scaling that has heretofore provided the "engine" for significant performance gain at each successive technology generation is running out of steam. Innovative strain engineering techniques such as SiGe and high-stress nitride overlayers have been introduced to "turbo charge" the transistor through mobility enhancement, and these techniques will continue to play an important role in device scaling. Likewise, for the transistor wiring, copper combined with lower-k dielectric insulators will continue to be required to fully leverage circuit performance gains. The need for additional levels of copper interconnect at each generation to co-optimize density and performance will also persist.

Overarching the technology trends that will be presented at this year's SEMICON West is the continuing emphasis on productivity and technology extendibility, as the industry continues to develop innovative solutions for an increasingly cost-sensitive consumer-driven end market.

Arthur H. del Prado, CEO & President, ASM International NV

One of the major challenges semiconductor device makers are facing today is power consumption, particularly in handheld devices and their so-called standby power mode, which causes batteries to leak current when the device is not in use. One of the most promising solutions for addressing standby power consumption is atomic layer deposition (ALD). This technology is winning more supporters as IC makers seek multi-generational solutions to optimum power usage.

ALD creates ultrathin films of exceptional quality and flatness. In the past few years, this technology has come of age, and it is now ready for implementation in the high-volume manufacturing of gate stacks that reduce standby power. Plasma-enhanced chemical vapor deposition (PECVD) is a process that replaces thermal with plasma energy to create more reactive species in the deposition reaction, so the placement of atoms on the wafer is faster. It also allows for greater versatility in selecting precursor molecules.

Manufacturers of DRAMs and RF devices, which both require capacitors with high density and low-leakage current, have all demonstrated the benefits of PECVD. For capacitor applications, the ion bombardment from the plasma can be used to increase the density and, with that, the electrical quality of the oxide layers. Together with the metal electrode layers for top and bottom contacts, unparalleled electrical properties have been demonstrated. In comparative tests, plasma ALD scores 1-2 orders of magnitude lower in leakage current than ALD.

What remains in ALD's development is to find a suitable integration path, and some of the top semiconductor manufacturers are indeed quite close, systematically removing implementation hurdles. Industry-wide adoption of enabling technologies like ALD will offer many benefits throughout our industry and beyond, as they offer a range of applications limited only by our imaginations.

André-Jacques Auberton-Hervé, CEO, Soitec

Two of the hottest topics at SEMICON West 2006 are bound to be power and design. Last year, the buzz was about the new metric: performance per watt. This year, tackling the power challenge has moved into high gear. One of the primary tools is design, and in this age of nanotechnology, design starts at the substrate level.

As SEMICON West approaches, chipmakers on the leading edge of the microprocessor world are focused on their design choices for the 45 nm node. At the heart of these designs are new and evolving ranges of engineered substrate solutions, including SOI, strained SOI and ultrathin SOI. Design innovations like embedded memory technologies leverage SOI for major die-area reductions. High-impedance engineered substrates for RF SoCs are now ready for upcoming device generations. Consistent with these trends, the overall engineered substrate market is in a very high-growth mode.

With the shift in drivers to consumer markets, however, the entire industry has to look at the big picture as never before. When we look at speed, we have to look at heat. When we look at performance, we have to look at power. When we look at manufacturing, we have to look at design. When we look at cost, we have to look up and down the line for the real impact. The fact is, when we look at the direction our industry is taking, we have to look at the entire R&D manufacturing commercial ecosystem. Fortunately, from the engineered substrates vantage point, the view is excellent.

Michael Polcari, President & CEO, Sematech

Long a fixture in executives' travel schedules, SEMICON West has emerged as one of the world's most educational and eclectic displays of cutting-edge microchip technology. From our perspective, the 2006 show — with its first-time

TechXPOTs focused on specific technology and manufacturing areas — will provide some of the best views yet. Here are some examples:

• Advances in lithography for the 45 and 32 nm technology generations, including defect detection and cleaning techniques for EUV mask blanks, and high-NA lens materials and high-refraction fluids for 193 nm immersion.

• Innovations in interconnect, such as development of CVD-based films with low-k effective, and explorations of 3-D modeling and other heterogeneous solutions.

• Breakthroughs in transistor scaling efforts, among them new materials for metal electrodes, MOSFET channels and multi-gate structures.

• Innovations in manufacturing effectiveness, including manufacturability assessments, fab and equipment productivity improvements, and advances in AEC/APC and e-manufacturing technologies.

• A first look at the 2006 update of the International Technology Roadmap for Semiconductors (ITRS), which will identify the barriers and opportunities affecting the above-mentioned technologies.

Most importantly, SEMICON West 2006 stands with other industry meetings in gauging and depicting our collective progress, and reminds us of the overriding importance of collaboration as an affordable means of clearing the R&D and manufacturing hurdles in our critical path. Working together to extend our current technology, build infrastructure for emerging technologies, and perform early exploration of the most promising alternatives is key to our industry's ability to generate the annual innovations that make SEMICON West one of the world's most fascinating expositions.

Craig Kerkove, Vice President & General Manager, Hitachi High Technologies America

With the semiconductor industry's push for ever-smaller geometries and continued advances in speed and power, equipment suppliers are forced to develop new or improved processes that enable their IDM or foundry customers to meet these evolving manufacturing requirements.

The numerous process and production challenges faced by the industry today force equipment suppliers to be experts not only in their own process technology, but also in such areas as materials science, IC design and process integration. For our company, the challenges extend into various IC categories. In logic, the push toward dual metal gate structures and integration schemes for 45 and 32 nm technologies requires the development of new materials, processes and process control techniques. Next-generation flash memory is creating a need for in situ high-k gate etch, with a focus on developing processes for a wide variety of high-k material options. DRAM manufacturers continue to push HARC etch to the extremes with even higher aspect ratio requirements. Finally, while these FEOL changes are occurring rapidly, BEOL interconnect levels are shifting to softer low-k and ultralow-k dielectrics, meaning additional development on the part of the equipment supplier.

This year, etch issues resulting from the industry's transition to 193 nm immersion lithography is one of the biggest challenges. Thinner resists can negatively impact CD uniformity and LWR/LER, and new resist profile problems are beginning to appear. This means that more selective etch processes and chemistries must be developed to cope with thinner resists.

The good news for the equipment industry is that we're seeing strong equipment sales growth this year and likely going into 2007, which will enable us to invest in continued product and process innovation to support our customers. Looking at the big picture, the industry is also increasingly recognizing its responsibility as a good corporate citizen, and is adopting initiatives to reduce energy consumption.

Moving forward, there are major issues surfacing around the adoption of 300 mm Prime and the need to start 450 mm programs — both of which will be costly and require cooperation and collaboration between IDMs and their suppliers.

Front-End Process Executive Viewpoints

Mark Namaroff, Senior Vice President of Marketing, Axcelis Technologies

It's no secret that manufacturing cost pressures remain at an all-time high; now more than ever, chip manufacturers struggle to keep new technology adoption in balance with real-world return-on-investment questions. It's a perennial problem, but the good news is that we're beginning to see process developments for the 65 and 45 nm nodes that not only deliver better device speeds and performance, but also offer advantages that help minimize these cost challenges.

One example can be found in the highly cost-sensitive memory device arena, where DRAM manufacturers are moving to dual polygate structures in order to improve device speed. Recent developments in the use of molecular implants, specifically in the use of ClusterBoron, promise dramatic benefits in improving low-energy implant productivity and reducing manufacturing costs. Moreover, this approach has shown specific advantages in enabling effective photoresist removal where other dual polygate applications, such as plasma immersion, lack sufficient cleaning solutions. In other areas, namely for source/drain extensions, molecular implants promise to simplify and eliminate process steps, such as pre-amorphizing implants, and allow manufacturers to use standard anneal technologies rather than having to adopt alternative methods, such as laser or flash annealing.

Moving forward, we expect to see additional advances in ion implantation, such as the continued use of hydrogen implants for silicon on insulator applications, carbon implants for enhancing transistor performance, and many others. We see these developments as the beginning of a new era in ion implantation, where emerging technology needs are met with simple, elegant solutions that promise the productivity and cost benefits necessary for long-term success.

Bob Havemann Vice President of Technology, Process Integration & Applications, Novellus Systems Inc.

Increased density and performance continue to be the key technology drivers for the semiconductor industry. However, growing cost pressures mean device manufacturers must look for new and innovative manufacturing solutions to realize aggressive density and performance goals at affordable cost.

For high-density memory devices, cost and manufacturability issues in the interconnect arena have collided to create an inflection point for conversion from aluminum to copper wiring, and this trend will accelerate as performance factors also come into play. Key factors driving this conversion to copper are the higher cost of scaling aluminum plug fill technology and high defect levels associated with the subtractive aluminum etch process. Another reason for this migration toward copper is because it's a better conductor than aluminum — an attribute that has enabled some companies to decrease the number of layers in their design for additional cost savings.

While density is also important for logic devices and will continue to drive improvements in dielectric and metal deposition technologies, performance is the ultimate measure of product value. The transistor scaling that has heretofore provided the "engine" for significant performance gain at each successive technology generation is running out of steam. Innovative strain engineering techniques such as SiGe and high-stress nitride overlayers have been introduced to "turbo charge" the transistor through mobility enhancement, and these techniques will continue to play an important role in device scaling. Likewise, for the transistor wiring, copper combined with lower-k dielectric insulators will continue to be required to fully leverage circuit performance gains. The need for additional levels of copper interconnect at each generation to co-optimize density and performance will also persist.

Overarching the technology trends that will be presented at this year's SEMICON West is the continuing emphasis on productivity and technology extendibility, as the industry continues to develop innovative solutions for an increasingly cost-sensitive consumer-driven end market.

Arthur H. del Prado, CEO & President, ASM International NV

One of the major challenges semiconductor device makers are facing today is power consumption, particularly in handheld devices and their so-called standby power mode, which causes batteries to leak current when the device is not in use. One of the most promising solutions for addressing standby power consumption is atomic layer deposition (ALD). This technology is winning more supporters as IC makers seek multi-generational solutions to optimum power usage.

ALD creates ultrathin films of exceptional quality and flatness. In the past few years, this technology has come of age, and it is now ready for implementation in the high-volume manufacturing of gate stacks that reduce standby power. Plasma-enhanced chemical vapor deposition (PECVD) is a process that replaces thermal with plasma energy to create more reactive species in the deposition reaction, so the placement of atoms on the wafer is faster. It also allows for greater versatility in selecting precursor molecules.

Manufacturers of DRAMs and RF devices, which both require capacitors with high density and low-leakage current, have all demonstrated the benefits of PECVD. For capacitor applications, the ion bombardment from the plasma can be used to increase the density and, with that, the electrical quality of the oxide layers. Together with the metal electrode layers for top and bottom contacts, unparalleled electrical properties have been demonstrated. In comparative tests, plasma ALD scores 1-2 orders of magnitude lower in leakage current than ALD.

What remains in ALD's development is to find a suitable integration path, and some of the top semiconductor manufacturers are indeed quite close, systematically removing implementation hurdles. Industry-wide adoption of enabling technologies like ALD will offer many benefits throughout our industry and beyond, as they offer a range of applications limited only by our imaginations.

André-Jacques Auberton-Hervé, CEO, Soitec

Two of the hottest topics at SEMICON West 2006 are bound to be power and design. Last year, the buzz was about the new metric: performance per watt. This year, tackling the power challenge has moved into high gear. One of the primary tools is design, and in this age of nanotechnology, design starts at the substrate level.

As SEMICON West approaches, chipmakers on the leading edge of the microprocessor world are focused on their design choices for the 45 nm node. At the heart of these designs are new and evolving ranges of engineered substrate solutions, including SOI, strained SOI and ultrathin SOI. Design innovations like embedded memory technologies leverage SOI for major die-area reductions. High-impedance engineered substrates for RF SoCs are now ready for upcoming device generations. Consistent with these trends, the overall engineered substrate market is in a very high-growth mode.

With the shift in drivers to consumer markets, however, the entire industry has to look at the big picture as never before. When we look at speed, we have to look at heat. When we look at performance, we have to look at power. When we look at manufacturing, we have to look at design. When we look at cost, we have to look up and down the line for the real impact. The fact is, when we look at the direction our industry is taking, we have to look at the entire R&D manufacturing commercial ecosystem. Fortunately, from the engineered substrates vantage point, the view is excellent.

Michael Polcari, President & CEO, Sematech

Long a fixture in executives' travel schedules, SEMICON West has emerged as one of the world's most educational and eclectic displays of cutting-edge microchip technology. From our perspective, the 2006 show — with its first-time

TechXPOTs focused on specific technology and manufacturing areas — will provide some of the best views yet. Here are some examples:

• Advances in lithography for the 45 and 32 nm technology generations, including defect detection and cleaning techniques for EUV mask blanks, and high-NA lens materials and high-refraction fluids for 193 nm immersion.

• Innovations in interconnect, such as development of CVD-based films with low-k effective, and explorations of 3-D modeling and other heterogeneous solutions.

• Breakthroughs in transistor scaling efforts, among them new materials for metal electrodes, MOSFET channels and multi-gate structures.

• Innovations in manufacturing effectiveness, including manufacturability assessments, fab and equipment productivity improvements, and advances in AEC/APC and e-manufacturing technologies.

• A first look at the 2006 update of the International Technology Roadmap for Semiconductors (ITRS), which will identify the barriers and opportunities affecting the above-mentioned technologies.

Most importantly, SEMICON West 2006 stands with other industry meetings in gauging and depicting our collective progress, and reminds us of the overriding importance of collaboration as an affordable means of clearing the R&D and manufacturing hurdles in our critical path. Working together to extend our current technology, build infrastructure for emerging technologies, and perform early exploration of the most promising alternatives is key to our industry's ability to generate the annual innovations that make SEMICON West one of the world's most fascinating expositions.

Craig Kerkove, Vice President & General Manager, Hitachi High Technologies America

With the semiconductor industry's push for ever-smaller geometries and continued advances in speed and power, equipment suppliers are forced to develop new or improved processes that enable their IDM or foundry customers to meet these evolving manufacturing requirements.

The numerous process and production challenges faced by the industry today force equipment suppliers to be experts not only in their own process technology, but also in such areas as materials science, IC design and process integration. For our company, the challenges extend into various IC categories. In logic, the push toward dual metal gate structures and integration schemes for 45 and 32 nm technologies requires the development of new materials, processes and process control techniques. Next-generation flash memory is creating a need for in situ high-k gate etch, with a focus on developing processes for a wide variety of high-k material options. DRAM manufacturers continue to push HARC etch to the extremes with even higher aspect ratio requirements. Finally, while these FEOL changes are occurring rapidly, BEOL interconnect levels are shifting to softer low-k and ultralow-k dielectrics, meaning additional development on the part of the equipment supplier.

This year, etch issues resulting from the industry's transition to 193 nm immersion lithography is one of the biggest challenges. Thinner resists can negatively impact CD uniformity and LWR/LER, and new resist profile problems are beginning to appear. This means that more selective etch processes and chemistries must be developed to cope with thinner resists.

The good news for the equipment industry is that we're seeing strong equipment sales growth this year and likely going into 2007, which will enable us to invest in continued product and process innovation to support our customers. Looking at the big picture, the industry is also increasingly recognizing its responsibility as a good corporate citizen, and is adopting initiatives to reduce energy consumption.

Moving forward, there are major issues surfacing around the adoption of 300 mm Prime and the need to start 450 mm programs — both of which will be costly and require cooperation and collaboration between IDMs and their suppliers.

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