Memories of 25 Years Gone By

Alexander E. Braun, Senior Editor -- Semiconductor International, 1/1/2004

This year, Semiconductor International celebrates its Silver Anniversary, and we use this happy milestone as an excuse to give our readers a look back at what the industry was like then, through the recollections of industry leaders who were just getting started on their careers in semiconductors when we began publication in 1979.

If you woke up in 1979, what would it be like? Much might seem familiar, but the differences would be profound.

Over that year on the news, Walter Cronkite described how armed Iranians rushed the U.S. Embassy, capturing Americans. Later that year, a U.S. envoy was killed in Afghanistan, President Jimmy Carter and Mexican President López Portillo discussed the illegal alien problem, and the Three-Mile Island nuclear reactor accident investigation was underway. China and Vietnam were fighting a border war, and there were concerns that the Soviet Union might intervene. The UN Human Rights Commission accused Israel of war crimes in occupied Arab territories, and there was a shortage of secretaries in the United States during that recession (college grads were advised to learn how to type as a way to get employment). After the newscast, you would be urged to stay tuned for "Mork and Mindy," "Soap" and, later, "The Johnny Carson Show." "I Love Lucy," as always, was in sempiternal reruns.

A brand new 64 kb DRAM, sitting on its wafer, circa 1979. (Source: Texas Instruments)
The very latest in furnace monitors, back in 1979-1982. (Source: Intel Corp.)

If you wanted to dress up, you could get a $119.90 three-piece suit, while ads for fur coats of every description would ensure that the lady in your life would look as snazzy as you did. You might fly Pan Am on business — it had introduced its Sleeperette seats. If you could afford an $89,900 mortgage, you might settle down in a nice suburban 4-bedroom, 2.5-bath home on half an acre in Long Island. In the evening, you would listen to your favorite tunes on your new 8-track tape player, and next morning commute in your luxurious $13,998 Peugeot.

At work, over lunch, you might peruse a brand new publication, called Semiconductor International, destined to become the industry's technical authority.

Inside, you would discover that Royal Zenith Corp. offered its Misomatic Autostep for step-and-repeating PCB negatives from the original, with 0.0002 in. accuracy. And that GCA Corp. introduced its DSW 4800 Direct Step on the Wafer System, boasting, "We're not talking about 3 µm, or even 2 µm geometries. We're talking 1.5 or 1.25 µm geometries!" Karl SÜSS had introduced a Submicron Mask Aligner with a uniform resolution of 0.4 µm, and alignment accuracy in the region of 0.1 µm, while Applied Materials touted its 7800 RP radiant heated epitaxial reactor (the Epitax Rex), which guaranteed film uniformity in the thickness range of 3-8, and 8-25 µm.

For this, our 25th anniversary issue, we asked a few industry leaders to reminisce about what our industry was like back in 1979 when, like us, they were starting out in the fledgling world of semiconductors. We hope you enjoy this trip down memory lane.

Retrospective Contributors

Daniel Queyssac	ASM America Inc.
Robert Doering	Texas Instruments Inc.
Paolo Gargini	Intel Corp.
Tom Seidel	Genus Inc.
Phil Ware	Canon USA Inc.
G. Dan Hutcheson	VLSI Research Inc.
Patrick Kiely	Electroglas Inc.
John Poate	Axcelis Technologies
Viven Krygier	Pall Microelectronics
André-Jacques Auberton-Hervé	Soitec
David Lam	Lam Research Group
Art Zafiropoulo	Ultratech Inc.
Jerry Coder	DuPont Electronic Technologies
Don Mitchell	FSI International
Jean-Marc Pandraud	Mykrolis Corp.
Bruce Freyman	Amkor Technology Inc.
Bob Reback	Cimetrix Inc.
Joan Koppenbrink	Rodel Inc.
Neil Kelly	LTX Corp.
Malcolm Cox	Royce Instruments Inc.

Some Thoughts While Riding Into the Sunset

Daniel Queyssac, Former President and COO, ASM America Inc., Phoenix, www.asm.com

I was fortunate to start my career in the semiconductor industry while it was still in its infancy. The growth was visible and unquestioned, and the industry behavior was exciting and irresponsible. It was a lot of fun. It was back then that the specific elements of our industry took shape. It was a stunning concept, except for the fact that Sam Walton already knew it: Offer more for less.

Unlike any other industry I can think of, we were all convinced that we could make better devices cheaper than the other guys and outsell them all. At the time, the more established companies such as RCA, Philco and Raytheon had a management that was quite traditional in their thinking and did not want to be part of this madness. They were promptly left behind.

Lester Hogan of Motorola and later Fairchild fame tells the story about Philco investing something like $15 million (probably equivalent to a quarter of a billion dollars now) to build a fully automated line, or what fully automated meant at the time, to manufacture metal alloyed diffused germanium transistors (MADT). MADT was considered state-of-the-art back then, and was used to make the discrete flip-flops in computers.

It took them a couple of years to finish the line, but they were very confident it would enable them to take over the market. As soon as the line was ready, they opened their Electronic News newspaper to learn about Fairchild's announcement of the first silicon planar transistor. Needless to say, this traditional industrial thinking did not bring about the results they were expecting, and illustrates what became the holy grail of the industry: Lead with technology and no worries about anything else.

The planar breakthrough was followed by the first integrated circuit, the first solid-state memory and the first microprocessor. Fairchild was the major innovator at that time, but was quickly replaced by Intel, which created the first commercial DRAM, UVROM and microprocessor. Presently, Intel still maintains both technology and product leadership in the industry.

This continuous stream of innovation was made possible by the exceptionally bright minds of the people employed in our industry, and the flow of capital attracted by the demonstrated and potential growth of semiconductor applications.

Unlike a lot of younger people, I do not take the current technology for granted. I can still remember when we had to load the boot sequence of the PDP11 mini-computer by flipping switches on the front panel. This, along with a teletype, was the full extent of the man/machine interface. During the short time that it now takes to download a file, several gigabytes big, from the web, I often think of when we were loading a few hundred bytes of program at 300 bauds from a perforated tape read by a teletype machine. We can now communicate with virtually anybody in the world securely and at the speed of light. What progress! And it was brought about by the electronics industry.

This is by no means the end. More mind-blowing applications are going to be made possible by the continuous innovations of high technology. But enough nostalgia, let's have fun and engage in the perilous exercise of crystal ball reading.

It is obvious, and I am certainly not the first one to point this out, that the semiconductor market cannot continue to grow at an average of 17% per year as in the past. Projecting such growth rates means that the market will be as big as the world GNP in 25 years or so. It is clear, however, that the pervasiveness of electronics will continue and result in a respectable average future growth rate in the high single digits.

We are now at the stage where the industry is maturing, and we have to be prepared for the fact that it will take a lot longer to go from a $100 billion market to $1 trillion market than it took to go from $10 billion to $100 billion. Additionally, the suppliers will break out into three distinct groups. The first group will consist of five to six companies with aggregated sales representing a third of the total market. They will have the 300 mm fabs and will lead the technology race. The second group will be a collection of 20 to 30 companies that will be niche players with average technology in highly specialized applications. This group will have sales of 30% of the market. Finally, the rest of the market will be covered by foundries with a technology level between group one and two, and 300 mm fabs.

In terms of applications, the new frontier will most likely be in bioelectronic micromachines that will crisscross the human body to fix all types of ailments. Electronics will supplement or replace motion fully integrated with the nervous system. It is not impossible to imagine that the famous man/machine interface will move to the level of reading the body electric signals, and direct communication will be possible between the brain and a distributed computer system. At the same time, silicon may start to be replaced by a more organic computing medium that would facilitate bio applications.

Like the 17% market growth rate, Moore's Law will not be applicable forever. But as the technology challenges multiply, so will the number of people assigned to solve the challenges and the amount of money applied to solve them. Moore's Law will apply for a long time, and molecular computing may further extend its validity deep into the century if one replaces the number of transistors by computing power. All this and other exciting areas that I do not have the wisdom to foresee are going to make the next 40 years in electronics even more exhilarating than the previous ones. It will be a different type of thrill — more structured and less spontaneous, but certainly as challenging and creative as it has ever been.

As for me, the journey from germanium transistor to the billion-transistor, 10 GHz microprocessor has been an opportunity I feel privileged to have been part of. It has been a great ride.

Breaking the 2.0 µm Barrier

Robert Doering, Senior Fellow, Silicon Technology Development, Texas Instruments Inc., Dallas, www.ti.com

I interviewed at Texas Instruments in 1979. At that time, a major challenge was shifting products into NMOS technology. PMOS had been around for a while, and NMOS was taking off. I started with SRAMs, and within a year I was working on DRAMs — memory drove business and technology then. I came at the tail end of the 64 kb DRAM development, but was on the ground floor for 256 kb DRAM development.

Lithography was a challenge even then. We were getting the first steppers, and didn't know if they'd do much better than about 2.0 µm resolution — about what we did with the best 1× scanners. The lab room that we built at TI for these steppers was on the first floor. We thought there'd be less vibration there than on the third floor, which was where we had our fabs. We called it the "2.0 µm Room" because we expected to break through the "2.0 µm barrier," but didn't know by how much. Soon, in the lab, we could print lines pretty close to 1.0 µm. In 1985, we got 1.0 µm into production.

Back then at TI, our nomenclature was different from everybody else's. However, coming from an academic position, I had to learn about the semiconductor industry almost from scratch, anyway. I'd been teaching at the University of Virginia and doing experimental nuclear physics since getting my Ph.D. in 1973. In today's job market, it's unlikely that someone with that background would be hired into the semiconductor industry — now we have electrical engineering departments that produce people with very specialized device physics knowledge. Then, companies doing semiconductor R&D hired physicists and chemists.

The atmosphere was more serendipitous and research units were smaller. For the first six months of the 256 kb RAM project, there were just two engineers. I was what was called a "process engineer" — today it'd be the device or process integration engineer — and there was also a design engineer. As we worked on big challenges like reducing the spacing between active areas, he and I were the 256 kb RAM team! Today, something as big as a new DRAM would start with many engineers assigned to it.

I mentioned how different the nomenclature was at TI because semiconductors grew up here separately and earlier than in what would become Silicon Valley. Silicon substrates were called "slices." ICs were "bars." "Moat" was the active area we were trying to get closer together. After learning the TI terminology, I eventually discovered at industry conferences that there was an entirely different nomenclature, originated in Silicon Valley, where they called these things "wafers," "chips," etc.

We new guys from academia were cautioned about what we said at conferences. It was justified. When I was in nuclear physics, my whole purpose in attending a conference was to explain my work in enough detail to enable anyone to reproduce and verify my results. Not a good idea when you have trade secrets and patents in the works. Information exchange was initially uncomfortable until we learned what was OK to talk about and what wasn't. Technical conferences tended to be smaller and hold more surprises. Of course, surprises still occur today, but back then there were more presentations you'd leave saying to yourself, "Wow, I didn't expect that!" Maybe it just seemed that way to us newbies.

In 1979, fewer of us were required to do the R&D. When I joined our MOS lab, I first had to learn how to "run a lot." I had to process it through the line by myself — learn to run each piece of equipment. There weren't dedicated operators for each tool. Normally, our techs would carry the material to a machine, run the lot, then move to the next machine. They taught me to do the same — for example, push-and-pull furnaces (done manually then), do the alignment (before the steppers were operational), and etch (which was mostly wet then), dunking stuff into tanks and doing cleanups. I also learned how to do layout, because you had to make your own test chip to develop new technology, with individual transistors, capacitors, "interconnect combs," and all the other test structures.

An engineer like myself, who worked on device physics and process integration, was responsible for designing the entire process flow. When working on the beginning of the 256 kb DRAM, the first thing I had to do was to go to the CAD workstation and draw all the test structures. Then I did a PG release to get masks made, and my technicians and I ran the material through the line, made all the measurements and produced the design rules and device models.

Even then, we were limited by lithography and new materials — some experimental metal films (like tungsten) refused to stick well to SiO₂, and would peel off the wafer. Getting good contacts was a persistent problem. We'd often find, when we put the metal down and probed, that many weren't open. Early plasma etching made this even worse. Wet etching was more reliable; you could squint through the microscope and see whether it was open or not. During over-etch, plasma etching sputtered material off the photoresist's edges down into the hole, or caused chemical reactions that deposited some polymer at the contact's bottom, which wasn't always visible. Through the microscope, it appeared as a nice clean contact hole, then you'd put the metal down and find there was some kind of barrier layer created by the etch.

In some ways, difficulty levels haven't changed. With 256 kb DRAMs, the process might have required only about 70 steps (depending on how you count) and one metal level, but we lacked today's accumulated experience and process knowledge. Today, products may have six to eight metal levels, perhaps 500 process steps, and deal with more materials. Back then, in the final product, it was only silicon, dopants, SiO₂, polysilicon and aluminum; today there are several silicides, all sorts of dielectrics, more metals (e.g., copper, tungsten), etc. Thus, today's complexity level challenges our experience, forcing us to learn more — but we're closer to hitting fundamental limits.

As far as silicon is concerned, today's defense market is almost a non-driver. Twenty-five years ago, there were efforts like the VHSIC program, on which a number of companies, including TI, had contracts. Thus, the work to develop many significant concepts, novel ICs, etc., was partly government-funded. There's little of that today, mostly in compound semiconductors, infrared detectors, and some display technologies. The silicon chipmaker's mainstream is barely affected by government contracts to industry. However, it's not at a level to have comparable impact to the university funding of 25 years ago. We probably need at least an additional $200M/year of university research on long-range IC challenges to help reach a new plateau beyond the perceived limits of CMOS technology. Electronics will need enormous breakthroughs to make as much progress over the next quarter century as we have made since 1979.

Post-Silicon Gate Possibilities

Paolo Gargini, Intel Fellow and Director of Technology Strategy, Intel Corp., Santa Clara, Calif., www.intel.com

In the 1970s, we realized that there was a possibility that the post-silicon gate — a self-aligning process — would be the way to go, although nobody expected it to last so long. All 1970s processes were primarily wet-etch-based and exposure tools of the time exceeded device physics. You could make smaller devices, but no one knew how to make them work. By the end of the 1970s, one could make a 10 µm gate. Another major innovation was HMOS, for 4 µm. The major lithography breakthrough was the Perkin Elmer because it scanned across the wafer, exposing it entirely — none of this one-die-at-a-time nonsense of today.

Towards the end of the 1970s, we were reaching wet etch's limit. We etched contacts and printed at about 3 µm. When we'd finish the wet etch, they'd be closer to 6 µm, because we'd etch so much on each side. With dry etch, if you opened something around 3 µm, you'd end with 3.5 µm or so — an incredible improvement! At Intel, we had the "Advanced Rear End" project. It replaced wet etch in the back of the process with dry etch steps, to go from 6 to 3 µm. Our best etch operator could read the wafer's color changes as it was etched, and pull it out at the right moment.

There was a struggle over how to make advanced MOS devices, because when we neared 2.0-1.5 µm, a few years into the 1980s, the hot electron effects became obvious: You could make the gate small, but the junction was so sharp that the electrons near the drain had so much energy they'd jump directly into the oxide. In the 1970s, we'd just gotten away with the process to avoid diffusion under the gate, which was really flaky, because it had spin-on arsenic. We'd take an arsenic-containing oxide and spin it on like resist. The oxide wouldn't fit very well next to the gate, and it would pull back. So diffusion started at some distance from the gate and then went through all the steps, progressing almost to the gate. Processes weren't as reproducible or controllable as they are today. Our old Mountain View, Calif., plant was in a commercial building, and there was no airflow control — if one day the humidity was higher, the process didn't work and we'd shut down.

Although we made microprocessors, for Intel the volume was in memory products — remember, the IBM PC wasn't introduced until 1981. At the end of 1979, I was head of manufacturing. There was an ongoing discussion on microprocessors vs. SRAMs — we hardly sold any microprocessors. Because microprocessors generally lagged one generation behind our memory products' technologies, we thought we might use some of the new processes. Intel wanted someone to accelerate the technology process and they offered it to me — "Do it for a couple of years," promised my boss, "then we'll move you to a real job in DRAMs or flash memories." I accepted on April 1, 1980 (appropriate), and a year later IBM announced its first PC using our 8088 as its CPU. We knew they wanted to make some sort of a PC, but it took us a couple of years to understand its impact. All we did then was the 286, which was technologically three years behind anything we had already done with DRAMs.

Where Would We Be Without CMOS and its Friends?

Tom Seidel, Executive Vice President and CTO, Genus Inc., Sunnyvale, Calif., www.genus.com

As I look back through the past 25 years, so many major milestones in wafer-process tooling are absolutely incredible and fundamental to this industry's success (too many to recite here). Consider the continuums across 25 years:

• Lithography, where optical engineering literally crushed the Rayleigh limit

• Advancing ion implantation through low-, medium- and high-voltage incarnations with very high throughputs.

• Deposition technologies diversified among PVD, CVD and ALD

• Thermal processing going from horizontal to vertical, and rapid thermal.

• The introduction of chemical mechanical planarization for multilevel metallization.

Along the way, we learned how to tool for various wafer-size generations, which is now manifested as multigenerational bridge tools.

In the late 1970s, I was in a development group at Bell Labs working on the "twin tub process" where n and p wells were fabricated with separate ion implants for isolation. During that time, we saw a significant move from NMOS with its power dissipation issues to CMOS. In the subsequent 25 years, we have seen variations and improvements, but nothing has proved better than using a driver and load transistor with CMOS for a logic function. In 1980, a key part of the CMOS process was epitaxial silicon and the latch-up limiting enhancement it provides for isolation (and epi's enhancement of defect control). Only recently has substrate choice moved toward SOI, but still using CMOS transistors.

The incredible thing is that data used to generate the first thesis of Moore's Law and the entire fruition of the law to date have all been done with CMOS as the industry's core process technology. We have been traveling down the curve of Moore's Law — changing design rules, using higher densities and obtaining dramatic performance increases with the same CMOS device architecture. Interestingly, CMOS was adopted roughly 25 years after the invention of the transistor.

There were other key advances in the realm of 25 years ago that were top industry-enabling milestones — advances that we could not have done without in making ULSI-CMOS possible. The availability of dislocation-free silicon was a key advance. I recall working in the mid-1970s on the passivation of dislocations in starting silicon and their effect on SSI yields. So, I put Dash's invention of using an initial rapid pull rate and necking down the diameter to achieve dislocation-free starting silicon in the Czochralski crystal growth near the top of the list of enabling milestones.

About 25 years ago, there was a very active and productive community that dealt with the control and minimization of process-induced defects — those from incipient impurities, oxidation processing, ion implantation, etc. — all driving defect densities to &10/cm² that further enabled ULSI with CMOS. To my recollection, the first 32-bit microprocessor (the Bellmac32) functionally yielded in the spring of 1982 using ~3 µm design rules.

I put the self-aligned MOSFET on my list of key enablers for ULSI-CMOS. The innovation of sidewalls and controlling spacing between source, drain and gate edges, and controlling Miller capacitance, is certainly on par with dislocation-free silicon when you look at LSI and CMOS from a distance. By the early 1980s, there was an established vision that many advances were going to be topological (i.e., finer and deeper or taller). This led to the onset of today's multilevel metal and deep trench capacitor technologies.

From my view today, the significant historical perspective is that today's industry had its origin about 25 years ago with CMOS and has been supported since by "friends of CMOS." The industry's success has come from the extension of well-established elements to which we have added a few modular but performance-enhancing creative improvements. Today, we are seeing a paradigm shift to new advanced materials (i.e., high-k in the front end, low-k in the back) for further extension.

Visionaries will brainstorm migration from CMOS to some future "X"MOS. But until we know what that will be, CMOS and its friends are likely to continue until something like the complexity of system-on-a-chip becomes a barrier again. This too will be solved.

The Perils of Chasing the Next Big Thing in Photolithography

Phil Ware, Senior Fellow, Canon USA, Irving, Texas, www.usa.canon.com

Twenty-five years ago, I was still working with contact aligners at Cobilt. The industry was just starting on the path to scanning mirror projection aligners and steppers. As a benchmark, Canon's first FPA-1500 g-line reduction stepper came out in 1984, and its first stepping scanner around 1997.

Today, it's a surprise to me how the perceptions of what was needed in the future for photolithography didn't play out to match what actually happened. Somewhere in the evolution of lithography, we lost this ability.

Initiatives to find a post-optical solution were started back with the transition to 1 µm design rules. Back then, from the early days of the U.S. Department of Defense VSIC program, no one could believe that you could build numerical apertures (NAs) large enough, or push optics further than 1 µm. This led to the earliest National Technology Roadmap for Semiconductors (NTRS), with its list of potential lithography solutions including everything but the kitchen sink. Many next-generation lithography programs were launched that over the years have proved to be fruitless.

The expert opinions and consensus views (if a consensus has ever really existed) that optics simply would not last today seems to have been so naive on the part of everybody involved.

Amazingly, we are now in a mode where we keep repeating the cycle. We do not have any better way of predicting the future method of lithography today than we did before 1990. Photolithography tool suppliers have few guidelines or indicators that they can use to allocate resources effectively so that they don't put R&D dollars into dead-end programs, like X-ray. Today, it is very possible that EUV, with billions invested already, could end up being another dead-end program.

Have we been able to trust industry roadmaps? Apparently not. Looking back at the 1992 SIA roadmap, the only options missing were 157 nm and immersion (157 nm was not a roadmap contender before 1999, and immersion not until 2003). Post-optical, next-generation lithography (NGL) was originally targeted for the 180 nm node, with X-ray listed as one of the most likely candidates. Subsequently, the insertion target for NGL has slipped six nodes to 32 nm and, after years of effort, 157 nm may ultimately be abandoned. The current best guess for the photolithography solution for the 65 or 45 nm nodes — 193 nm ArF dry with super-NA lenses or wet with immersion optics — has never been listed as a potential solution for these nodes on any roadmap prior to 2003.

Have we been able to trust the consensus of experts that come out of workshops? Apparently not. The series of NGL Workshops (from 1997 to 2001) that winnowed down options for suppliers to focus on chose SCALPEL (an e-beam technique) and EUV, not 193 nm immersion. At any point in the past, expert opinions have always been too pessimistic toward the extension of optical lithography and too optimistic for NGL solutions. Consider the 1997 SEMATECH e-beam direct-write and electron, ion and photon workshops that evaluated all possible candidates for the 130 nm node, except for the extension of 248 nm, which turned out to be reality in 2001.

Have we been able to trust the roadmaps from chipmakers? Apparently not. Since the early 1990s, chipmakers have often claimed that they are at an advanced node when, in fact, actual devices being fabricated in their factories typically do not have any features of that nominal node size. In reality, there is little or no relationship between dense half pitch and many chipmakers' node definitions. This pseudo node acceleration creates a perception that photolithography suppliers' tool development schedules are always behind. For example, some chipmakers are already asking for firm 193 nm immersion delivery dates even though 193i has never been listed on any prior roadmap.

I have come to the conclusion that there are perils in chasing the next big thing in photolithography. All the industry indicators have been plotting paths that have made it almost impossible for tool suppliers to decide what technologies are real. In the absence of a clear indication of which method chipmakers might actually pick, tool vendors are being forced to fund multiple development programs simultaneously, some of which are likely to be mutually exclusive. Somewhere in the past evolution of photolithography, we put the cart before the horse. The result is that today roadmap acceleration now has the next three ITRS technology nodes arriving faster than any of the shorter-wavelength lithography tools. They say hindsight is 20/20, and I'm betting it will be equally interesting to look back to today some 25 years from now.

Technology Barriers: The Breakfast of Champions

G. Dan Hutcheson, President, VLSI Research Inc., San Jose, www.vlsiresearch.com

When I first heard that it was Semiconductor International's 25th year of covering the chipmaking industry, it prompted the memory that I had also started in this industry 25 years ago, in the week after Christmas of 1978. My father had enticed me into the industry with the challenge that no one had ever been able to forecast this industry. Like many, I cut my teeth on those early issues of Semiconductor International. The similarities between now and then are striking, and point to a brighter future than many may think after such a dark period.

Back then, the industry had just come out of its worst downturn ever, and everyone was fearful of another deep downturn. The downturn of 1975 had deeply scarred the industry's infrastructure and left most industry executives very cautious of expansion. There were many pessimists. The industry faced the so-called "One Micron Barrier" at which optics would supposedly fail to work. If it were crossed, chips would soon fail to work. Gordon Moore had revised his famous paper in 1975, stating that density would now double only every 24 months for the same cost, not the 12 months originally forecast in 1965, and some were predicting that Moore's Law was about to come to an end. Meanwhile, there was lots of new technology coming to manufacturing: wafer steppers, ion implant, plasma etchers, automatic wire bonders, and VLSI testers to name a few. Many questioned that they would work or that it could all be integrated in time for the transition to VLSI scales of integration. We wondered back then if the industry could ever reliably build chips with 100,000 transistors. We didn't call them red brick walls. They were called barriers, and most everyone saw barriers to the future everywhere. Yet, they were all broken down.

The lesson to be learned from this is not to be overly concerned with the issues of the present — that technology barriers always loom and seem fearful because the answers are unknown. The answers must come from breakthroughs. But technology barriers are eaten for breakfast by technologists. It is amazing to think how many barriers have been chewed up by the bright people of this industry over its history. Highlight a red brick wall to an engineer or scientist, and it's like a red cape to a bull — the main difference being that legions of technologists rise up to figure out how to tear these walls down. Those red brick walls represent nothing but opportunities for those that can overcome them. Moore's Law is not dead, and it won't be dead until this industry's technologists run out of ideas. I doubt that I will live to see that day.

The Changing Face of Equipment Sales

Patrick Kiely, Vice President Global Sales and Service, Electroglas Inc., San Jose, www.electroglas.com

Before taking a sales position at KLA Instruments in 1987, I worked for Tektronix, an instrumentation company that prided itself on extreme accuracy, with calibration to national lab standards and consistent, reproducible measurements regardless of location or operator. So when I started selling inspection equipment to chipmakers, I was astonished — the range of acceptable yields and measurement results was much broader than that experienced in electronics.

In those days, 50% device yields were still considered good, and measurements were often less repeatable or reproducible. No one seemed to have a consistent methodology to deal with linewidth or CD variation, or the differences in reflectivity on different device layers; there was a huge spectrum of allowable values. I was amazed that any working devices got made, but I learned that the situation was OK as long as our metrology tools could make some sort of improvement, and be delivered on time.

The biggest difficulty was getting a handle on what was going on in the fab. A customer would show us wafers, but we didn't know if we were looking at the worst case or the best case. Our approach then was to look at what each customer was presenting and find a way to excel at that, with the assumption that we could then excel in their production environment. But the excursions were much wider than anything we see today, so we had to sell technology capabilities.

I can almost pinpoint the moment when this attitude changed. In 1996, after I had joined Tokyo Electron Ltd., I was involved in several projects where our main pitch was to differentiate the technology we were offering — a tactic we had used successfully in the past. In each case, we finished our presentation, and the customer said something like, "OK, but we want to see reproducible results in the manufacturing line." Prior to this, every chip company had its own homegrown method of proving that a piece of equipment would work, but right around that time, the proof process got more consistent and disciplined across the industry. And it struck me that the concept of leading with technology was going away.

That's when today's model started to evolve. The typical approach is to lead with a solution to some manufacturing problem — customers want to talk about results and consistency. And if they say, "Hey, that looks neat," the next step is for them to ask how we did it. The technology is of interest, but it's not the first thing.

At the same time, the sales process has broadened way beyond a particular piece of equipment. Today, a customer is making a decision about your entire company — your factory, your supply chain, your documentation, the way you hire and train service reps. Some won't buy from you without an audit of all these functions. In a sense, this is also about repeatability and reproducibility: Can you stay healthy in different business cycles, keep operations tight, and quickly respond to problems when they crop up in different places around the world? One big driver is outsourcing — when the customer is likely to transfer responsibility for a product or process to a third party, everyone in my supply chain must be ready to deliver to a different account at a different location.

From a practical point of view, this means that the salesperson can't be a lone ranger. You need to prove the company's ability to work as a team, so you need high-level people from technology, service, manufacturing, and the executive suite involved in the sales process. And when you do a presentation, the content has to be real work product; the same information you use to run your company, to show that you have a process in place and use it. Everyone has to step up.

But, despite the extra work, and the challenge of adapting to the constant changes, I haven't ever regretted my move into the semi equipment business. It's the most exciting industry I've been in, and is filled with interesting, creative, intelligent, motivated people, who continue to astonish me with what they accomplish.

The History and Challenges of Ion Implantation

John Poate, CTO, Axcelis Technologies, Beverly, Mass., www.axcelis.com

It's amazing what can happen in 25 years. Take the ion implantation market, for example. In 1978, this sector was in its infancy — the first independent implant machine manufacturers had just begun to open their doors for business.

Two decades of R&D at major device houses, laboratories and universities had proven that ion implantation, with the concept of masking and self-alignment, was perfect for the emerging IC industry. Controllable doping could not be achieved by deposition and diffusion technologies; ion implantation was the way to go.

Today, ion implantation represents a $645 million market, according to Gartner Dataquest, and it's still growing. Since 1978, ion implantation equipment manufacturers have shipped over 6000 machines, of which about 4000 are still in operation. The present generations of implanters are the most productive and controlled machines in the IC fab, with throughputs that can be in the vicinity of 300 implants per hour, and with unrivalled process control. The industry has come this far through the close collaboration of implant machine designers and IC device designers and manufacturers. For example, in the 1980s, two device imperatives were recognized by the implant industry: high-energy implantation in the MeV region for laterally scaled well formation, and high-tilt, medium-current implantation to control short channel effects. Today, new high-productivity multiwafer implanters actually combine several well and channel implants into a single step, significantly reducing cycle time, while the latest-generation medium-current systems greatly reduce the components of angle variation to improve process control for high-tilt implants.

More recently, remarkable changes have occurred in the high-current machine class. Each successive node of the roadmap has not only demanded lateral shrinks, but also vertical shrinks for junction formation. For the 45 nm node, energies as low as 500 eV may be required. Transporting such low-energy ion beams with useful beam currents requires fundamental advances in neutralizing techniques to control space charge effects. The economic imperatives of IC manufacturing have, in many ways, imposed harsher constraints on the implant equipment industry. Across the spectrum, ion sources, end stations and control software automation have to be more productive and reliable. So far, we've met every one of these challenges head on — and succeeded.

Things continue to appear bright for implant from the roadmap perspective. In the early 1980s, ICs typically required five implants. Now, they often require 30 or more. To meet the physical challenges of the roadmap, different device architectures, such as double-gate and vertical structures on SOI substrates, are being investigated. These new structures will almost certainly require more and different implant steps. Indeed, the SOI substrates themselves are made by implantation techniques.

The implant industry in the United States has flourished because of close coupling between industry, national laboratories and universities. These interactions have now changed. Silicon-related research has diminished significantly in the universities and national laboratories. This decrease in research reduces the underlying knowledge base and the supply of skilled scientists and engineers.

Within the industry itself, there have also been major changes. The dialogue that existed in the past between the IDMs and equipment manufacturers was essential for the development of the next-generation machines. Now, as the fabless IC model emerges, we'll have to ensure that we continue this dialogue with foundries, and equipment manufacturers will likely take on more and more basic process research to ensure that we continue to clear every process and economic hurdle we encounter in IC manufacturing moving forward.

An X-Chromosome Perspective

Vivien Krygier, Senior Vice President, Marketing, Pall Microelectronics, East Hills, N.Y., www.pall.com/micro

When I look back over the past 25 years, I am in awe at what we've accomplished as an industry. Today, we can squeeze a billion bits of data into an area no larger than the face of a penny — all because of the tools we build, the materials we create and the technologies we invent. It's this sense of accomplishment and progress that keeps me coming to work every day.

We all know that the rate of technology development in the semiconductor industry far outpaces most industries; rapid-fire innovation is a hallmark of this business. Yet when I take a closer look at the past two decades, I see that other (perhaps more subtle) changes also shape and define our industry.

As a young woman starting out in the semiconductor business in 1977, I felt a bit like a pioneer. I didn't have many female colleagues then, and I think those of us who chose this field had to work harder and know more about the technology, products and industry than our male counterparts — that is, if we were to move up in our careers.

This is changing, but slowly. A recent study sponsored by IBM, Intel, Dell and Microsoft found that women's advancement in the high-tech industry has not kept pace with the rate of technology advancement. And, while there are more women in higher-level positions today than there were 25 years ago, women still represent a minority of the entire high-tech workforce — around 10-15%, according to numerous estimates. At the chief executive level, I can think of only a handful of women who hold leadership positions in the semiconductor business.

When I look around, I do see more women in semiconductor-related sales and marketing positions, but not as many as I'd like to see on the engineering side. At Pall, for example, the top two sales positions in Malaysia are now held by women. On recent trips to visit customer fabs in Malaysia and Korea, I was pleased to find engineering staffs comprised of a surprising number of women in their 20s and 30s. While this still isn't the norm today — not even in the United States — it is progress.

There is also a palpable change in the underlying mood of the semiconductor industry. Back in 1977, I was involved with many aspects of Pall's business — giving me insight into the pharmaceutical, food and beverage, and semiconductor markets. I fell in love with the semiconductor industry's collective sense of optimism. I, along with my coworkers and colleagues throughout the industry, had faith that the best was always still to come, that many days of prosperity and growth lie ahead.

Today, we're too focused on the cyclical nature of our industry. We obsess about the cycles; we are acutely aware of the changeable nature of our jobs. And this makes us less optimistic — or perhaps more realistic — about the long-term prospects for our industry.

But I do remain optimistic. The one thing that hasn't changed in 25 years is an overwhelming and infectious can-do attitude in the semiconductor industry — no matter what challenge we face. Because of this, our success has been — and continues to be — amazing, incomparable to any other industry I know.

In Just 20 Years: An SOI Journey

André-Jacques Auberton-Hervé, President and CEO, Soitec, Bernin, France, www.soitec.com

Things have changed a lot since I published the industry's first paper on ultrathin, fully depleted SOI at IEDM in 1984. The fall of the Berlin Wall and the end of the Eastern Bloc soon prompted the industry to look for new, civilian applications for promising technologies such as SOI that were, until then, stuck in a military and aerospace niche. Working with LETI and Thomson in development and industrialization of CMOS technologies, I was in charge of a European program to demonstrate how SOI could be of interest in applications targeting speed and performance. We were at the 0.7 µm node.

Today, SOI is a $162 million business, expected to grow 40% as an average in the following years (according to industry analysts), with a bright and certain future. Yet it was just over 10 years ago that my partner Jean Michel Lamure and I founded Soitec, convinced of the potential of SOI to get the industry through the silicon roadblock then predicted for the end of the '90s. At the beginning, it was a fairly lonely road. We had to evangelize the opportunity for exploiting SOI in high-performance applications, hopefully maintaining the support of customers in SOI military and space applications like Honeywell.

In the mid-90s, the suitability of SOI to address applications that are sensitive to power consumption became manifest with the dawn of the high-mobility world (later referred to as the nomadic electronic age). But the real trigger occurred a few years later, when the trade-off between high speed and power consumption became obvious. This revelation occurred at the same time that copper removed the interconnect bottleneck, returning transistor design issues to center stage for the performance race. Transistor design became the limiting factor in addressing speed, but also for solving the power consumption issue.

Shortly thereafter, IBM picked up the SOI-evangelizing relay, and our road didn't stay lonely for long. We were joined by Motorola, AMD, Sony, Toshiba and others, all promoting SOI.

With the coming of the millennium, the discourse changed dramatically: It was no longer a matter of "if SOI"; now it was "when SOI." At IEDM '99, those of us in the raw material arena joined the IC makers and equipment vendors as we created this new engineered substrate segment.

Of course, we then ran into this very long downcycle. Far less affected than other industry segments, we at Soitec managed to use the time to further develop our industrial capacity and product lines to meet the rapidly evolving needs of our customers. That said, while three years of tough times bring a lot of conservatism, the confidence that the success of this industry relies on innovation remains. The early adopters of SOI technology started using it at the 180 and 130 nm nodes. With the upturn, these pioneers will enjoy the benefits of SOI in volume production. They'll continue the scaling, putting more and more applications on SOI. The rest of the industry will join at the 65 and 45 nm nodes.

The more the scaling, the greater the need for engineered substrates. The demand for SOI and new options like strained SOI will increase for high-performance applications, but also for power consumption, which has now become a bigger issue for the industry. SOI is a unique solution in that it solves both the quest to maintain Moore's Law and at the same time keeps power consumption at reasonable levels.

The next stage is convergence. SOI is the right platform for implementing system-on-a-chip (SoC) in a cost-effective manner. The technology can cover both the very high-frequency requirements of RF as well as the requirements of logic. With SOI, they can be built on the same structure without bipolar CMOS. This reduces the number of mask steps by about 10. Since you don't need all the additional masks to do RF, SOI enables you to move faster and more cost-effectively into SoC.

But the SOI future is not just about the convergence of electronic functions like RF, analog/digital and power. It's also about putting MEMS side-by-side with logic circuits. In the very long term, we can envision the convergence of biotechnology and electronic nanotechnology, providing solutions for both worlds.

Coming back to today, though, our key challenge now is to integrate all the necessary technology innovations that allow the industry to maintain Moore's Law. That's where a new partnership paradigm is emerging: a trinity of IC makers, equipment vendors and raw material innovators like Soitec. This trinity is required to develop the 90, 65 and 45 nm nodes because the cost of missing the new technology targets is too high for the industry.

Fortunately, the industry today is quite convinced of the need for these partnerships in the rapid introduction of new materials in very complex new technologies. With three major transitions — the move to the sub-90 nm generations, 300 mm and new substrates — we are working together to accelerate the pace at which innovation reaches the end products that keep opening our new frontiers.

Becoming a More Specialized Industry

David K. Lam, Founder, Lam Research Group, Fremont, Calif., www.lamrc.com

Lam Research formally started in 1980, but it was conceived in 1979. We were small, almost cottage industries; back then, Applied Materials did about $50M in sales. The industry grew slowly because leading chipmakers — for example, IBM, Intel and Texas Instruments, where I worked — built their own equipment; they considered it a competitive advantage. Around then, they began realizing that this wasn't their core competency, and that they should focus on making chips instead. They were now willing to work with equipment companies, and the equipment industry began growing. I started Lam Research based on the opportunity I saw for plasma etching to go into production. It had been in R&D for some 10 years, with little production; the equipment wasn't yet sufficiently reliable to gain the confidence of the fab managers, who were ready to move to &5.0 µm circuits.

Fortunately, the recession ended in 1982, we had a wonderful 1983, and went public in 1984. We were one of the few early IPO semiconductor companies. It's been said it was easier to be a start-up then — this is true and false. True in that we were perceived as an emerging industry, and there was more willingness to invest, compared with today. Some investors think we're too mature, and too dominated by a few market leaders. They worry that big companies can easily crush you. They forget that there are always leaders, and a continuous need for innovations from start-ups.

During the late 1970s, early 1980s, anyone starting an equipment company tried to make the complete tool — designed and manufactured it, sold and supported it. Later, some companies (including Lam) realized they didn't have to do it all — they could buy a platform and other subsystems, and put their process module on it. Brooks Automation came into existence selling platforms, Cymer producing lasers for lithography system manufacturers, MKS making pressure gauges and flowmeters. Over the years, several subsystem companies came into their own, went public, and did well.

Today, because the industry is mature and more money is available, you need an angle. For instance, equipment manufacturers are beginning to also sell materials for their proprietary processes, or may sell services rather than tools. Everyone's looking to add value for the customer. Some of this resulted from customer base changes. During the downturn, many companies discarded much of their in-house expertise, and increasingly rely on suppliers for it.

In 1979, the engineer was more of a generalist; he knew something about everything. His 2004 counterpart must specialize and focus on one technology aspect. This results from the increasing complexity of everything in the industry. The importance of technology sectors has shifted, and once vital areas aren't as crucial. Who'd have thought that such a dirty process as CMP would enter the cleanroom?

We've tried to go from wet to dry processes mainly because of circuits' decreasing feature sizes, but we were also relieved that we would not have to deal with a lot of liquid chemicals — with copper we've come full circle. Because copper deposition is an electrochemical process, we're dealing with liquid again, as well as a messier environment. Ironically, it's a sign of progress as we work to replace aluminum with copper and go to lower-k dielectrics and use planarization techniques.

A Plea for a Return to Risk-Taking

Art Zafiropoulo, President, Ultratech Inc., San Jose, www.ultratech.com

In 1979, I ran a division that made plasma devices for semiconductor etching and stripping products. I left in 1980 to form Drytech. In 1979, worldwide, there were about 50 companies in the plasma sector. Then, Applied Materials wasn't involved in plasma etching. Perkin Elmer was the largest lithography company, with projection mask alignment technology. In 1978, GSA shipped its first reduction stepper, a 10:1, to Hewlett-Packard. Thus, in 1979, the industry began using reduction steppers, but the main production application was projection mask alignment. Three companies were involved — the leader was Perkin Elmer, Canon in Japan, and a company called Cobilt, which later went out of business, but had then sold six machines to General Instruments. I founded Ultratech Stepper in 1979, so we're also celebrating our 25th anniversary. As we became more diversified with laser processing tools as well as lithography, we changed the name to just Ultratech.

In those days, the engineer had wider access to decision-making management. If you wanted to visit with Walt Corrigan, Gordon Moore or George Wells, access was easy. You could tell them you wanted a shot at trying something you had thought of, and you'd usually get a go-ahead. The technology then was more of a black art than a science; today it is down to a science and process. You could by a litho system for under $200,000, so the risk factors weren't as great. Today, when a stepper costs $10 million or $15 million, it's a different matter — the risks are greater.

Management today is risk-averse. The industry is more structured, disciplined, with more capital investment. Therefore, risk is reduced and people tend to be followers, with fewer leaders willing to take risks with new things — those making decisions tend to be timid. That's why now it takes longer to implement and introduce new technologies.

Today's engineer better understands the science involved. Back then, there was more experimentation. The 1970s engineers were better experimentalists, while today's are better theoreticians — equally smart and capable. We probably worked longer hours — things were more challenging and we had a wider range of authority. Now, engineers are more specialized. It wasn't until the mid-1970s that such a thing as a plasma etch engineer (with a business card) existed. Everything's more businesslike now, and we've lost much of the fun. It's a more professional environment, with fewer personal relationships. There are more operational than visionary people.

We should be more willing to take a few calculated risks. This would benefit the industry's future. We've become wimps. There is fear of investing money, fear for job security, and so on. For many of us, our work and hobby were the same thing. Few can say that today.

The Good and Bad of the Old Days

Jerry Coder, President of IC Fabrication Materials, DuPont Electronic Technologies, Research Triangle Park, N.C., www.dupont.com/et

I started in 1976, when contact printing was the workhorse and scanning projection systems were being introduced. We were moving from negative to positive resists, and much of that resulted from the coming and adoption of projection printing systems. Shortly after, wafer steppers were introduced.

What struck me most when I first came to the industry was its unprofessional sales organizations — like used car salesmen. Companies were mostly driven by technologists, and were immature in their sales techniques. At SEMICON shows, they'd hire good-looking models ("booth bunnies"). A company hired one to streak the show, and she sauntered through the hall with the product's nomenclature on her buttocks. Everyone thought it referred to a booth number and kept searching for it. SEMI wasn't amused. Now everything is different, and professionalism — in terms of equipment and materials manufacturers, marketing products and customers — is high.

Business was strongly centered around IDMs, and foundries weren't part of the environment. Each company did process development — there were no consortia. Technology drivers centered more around memory than microprocessors. Intel was just coming into its own. I remember when the Japanese began taking over the memory market and everybody feared that they would drive the technology.

Much of the work was based on building relationships and long-term partnerships. Today, everything is much more business-oriented. The corporations one sells to are larger, they have purchasing professionals, and they have materials development groups. Before, you worked with the managing engineers. Now you're somewhat removed and the process has become formalized; it's lost some of its humanity. As suppliers, we worked and played hard — now, it seems there's only work.

Ushering in the Next Generation of Talent

Don Mitchell, Chairman and CEO, FSI International, Chaska, Minn., www.fsi-intl.com

Looking back, it's difficult to believe that we witnessed, first hand, the greatest invention of the 20th century. Others might argue that there are other technologies that merit this distinction. But for my money, it's the chip, which has enabled everlasting change in the way people live and has led to dramatic improvements in communication, standards of living, and the protection of natural resources. The chip has changed the world in ways we never could have imagined. I am proud to say I've been among the countless men and women that played a part in its development and growth.

I started out on the materials side of the business, in specialty chemicals, in the late 1970s. Back then, capital equipment and materials businesses were run in a much less formal way. Our company was managed by a group of 20- to 30-year-old managers. We used to take advantage of every occasion to celebrate — the first order of the quarter, the first payment, a big shipment, the launch of a new product. Despite our individual business responsibilities, any one of us would frequently be called upon to install equipment, solve a problem at a customer site, or work the tradeshows. It was a different business model than exists today. Sophisticated market analysis was in its infancy. New product ideas were serendipitously developed, concepts frequently drawn on restaurant or bar napkins, and then validated by customers over a beer.

Direct communication with customers, especially those located in other countries, was much more of a challenge. Teletypes, followed by fax machines, were the technology of the day. Instantaneous communication outside of the home country was a rarity.

As a consequence of the difficulty in communicating, customer interaction was much more relationship-focused than it is today. When customer visits occurred, we'd spend days together as opposed to a few hours. Because we spent that much time together, we would often combine business with social and recreational activities. We would never travel for a single meeting as we might today. Trips may have lasted for several weeks, and this extended time together really helped to build and secure relationships.

I represent the second generation of the semiconductor industry. The first generation consisted of the inventors — the people who were making discrete devices that came out of Jack Kilby's lab, followed by the IC designs of the '60s and '70s on 1-3 inch wafers. Simultaneously, the inventors of process equipment and materials technology focused more on process capability rather than control and repeatability. The second generation has focused on the commercialization of these dynamic technologies, adding discipline to manufacturing, marketing, quality and service processes. We evolved an informal business model and took it public. This generation has added a level of global sophistication while advancing technology. The next generation of leaders will need to be savvy business professionals and technologists who must further advance the business model to address the conflicting needs of ever-increasing technology investment in a climate of slower growth, punctuated by severe economic cycles.

Young people who are joining this business today will probably not have the same opportunities we did in the late '70s in terms of diversity of job roles and the celebratory culture of that time. The days when one person had such wide-ranging responsibilities within most companies are long gone in this age of specialization. On the other hand, the young men and women joining our industry today bring with them a level of technical qualifications and cultural diversity that will enable strong stewardship for our industry over the next 25 years.

Keeping Up With Changing Business Dynamics

Jean-Marc Pandraud, President and COO, Mykrolis Corp., Billerica, Mass., www.mykrolis.com

Over the past 25 years, Mykrolis has witnessed extraordinary change in the semiconductor industry. Our company — or I should say the various organizations that over time gave birth to what is now our company — has undergone considerable change as well. In the late 1970s, we were a subset of the Industrial Process division of Millipore Corp. Later we became the Microelectronics division of Millipore Corp. Only in August 2001 did we separate from Millipore, a company best known for its pharmaceutical, analytical, life science and water purification offerings.

The ever-changing dynamics of the industry have created an interesting and unique, if not challenging, environment in which to do business. Among the more notable of these dynamics has been the tendency for companies to spin off business units or ancillary divisions in efforts to concentrate resources on core markets. Another distinct trend has been the focus on multinational expansion, particularly in Asia, where China has become fertile ground for new subsidiaries. And, not surprisingly, investment capital has also weighed heavily on the development of the semiconductor industry.

Companies have gained greater focus. Years ago, it was not uncommon for companies to develop products that could be used in the semiconductor industry as well as in other markets. Because of rapid advancements and stringent controls in semiconductor manufacturing, however, these companies eventually found themselves developing separate product lines for semiconductor applications. Millipore, for example, had to develop a new line of filters for its semiconductor customers to accommodate their demands for finer pore sizes and more demanding chemical compatibility. In many cases, supporting a different line of semiconductor products and coping with higher cyclicality proved extremely challenging and, as a result, many companies have decided to focus their efforts on a single industry.

Multinational reach and expansion have become critical to success. In the late 1970s, North America and Europe were home to some of the most vibrant semiconductor companies in the world. Over time, these companies had to deal with new entrants seeking more lucrative opportunities just emerging in the Far East — first in Japan, then in Korea, Singapore and Taiwan, and now in China. Gradually, political borders once impenetrable to foreign industry, sometimes for very strategic national-interest reasons, vanished. To compete today, a global presence in no fewer than 10 countries is an absolute requirement, as is complete understanding of the cultures in which you do business.

The industry has developed a reliance on investment capital. As the nucleus of the technology industry, semiconductor companies have always required a fair amount of capital investment to enable the manufacturing of smaller and more powerful electronic devices. With the rate of technological change accelerating and more semiconductor manufacturing moving to a foundry model, the challenge will be to increase the return of investment capital by raising yields and lowering costs, while maintaining the flexibility to satisfy a variety, even a proliferation, of sophisticated new products demanded by consumers.

In addition to these dynamics, we've also seen competition escalating, becoming fiercer throughout the industry. "Do more with less" and "on time rather than sooner or later" are the new paradigms. We've reached the point where every step of the sales process for technological products counts — from order placement and execution to service and support. As companies streamline their business models and as they expand into new markets and compete for accounts, we should see these dynamics continuing their irreversible shift toward worldwide, ubiquitous, high-quality products and services over the coming years.

The PBGA Evolved to Take the Industry by Storm

Bruce Freyman, Executive Vice President of Operations, Amkor Technology Inc., Chandler, Ariz., www.amkor.com

In the late 1980s, I was fortunate to be leading a team of talented scientists and engineers at Motorola in Plantation, Fla. We were working on the invention and development of the plastic ball grid array (PBGA) that today has been widely adopted for IC packaging.

The PBGA has had a major impact on technological and economic evolution in the semiconductor packaging industry. Until the early 1990s, most semiconductor companies anticipated that quad flat packages (QFPs) would evolve to increasingly higher pin counts and finer pitches. This would lead ultimately to the industry’s migration to tape automated bonding or flip-chip mounted directly to a motherboard. PBGAs changed the course of the semiconductor industry by creating a new packaging technology roadmap based on laminate array packaging.

PBGAs increased the importance and role of the outsourced assembly and test industry. Before PBGAs, IDMs had always been the driving force behind the adoption of new packaging technologies. This changed when PBGAs became the first of many new packaging technologies commercialized by the outsourced assembly and test industry. The introduction of PBGAs played a major role in leveling the balance of assembly technology power from Japan — the traditional technology leader in packaging — to North American and European semiconductor manufacturers and the subcontract assembly industry.

When we were working at Motorola, our focus was to implement PBGA technology into Motorola's portable communications products. The first publication of this work was a paper presented at the 1991 Electronic Components Technology Conference in Atlanta. This paper created tremendous interest from Amkor's customers. Shortly after, I joined Amkor as director of PBGAs — a new position. During 1993 alone, Amkor introduced this technology to more than 50 major semiconductor companies, including every PC chipset, graphics and ASIC supplier. The resulting programs generated more than $100 million in assembly revenue for Amkor in 1995.

During 1993 and 1994, the development and manufacturing team at Amkor set standards for PBGA design and low-cost manufacturing that are still used today. In addition, Amkor continued to do development work that enhanced the application of PBGAs.

With Compaq Computer, we developed the first 27 and 35 mm PBGAs to package ASICs for the PC industry. These new designs were also the first to take advantage of the PBGA's potential for superior electrical performance; placing power and ground connections in the center created lower inductance. These packages are the highest-volume PBGAs in the world today.

With Sun Microsystems and LSI Logic, we designed the first four-layer PBGA to produce superior electrical and thermal performance for use in high-end computing applications.

Amkor developed the first application of PBGA mold degating using a plated gold runner on the PCB. This allowed the first use of conventional automolds for PBGA production.

We changed the PBGA PCB fabrication sequence from a "solder mask over gold" process to a lower-cost, higher-performance "solder mask over bare copper" process. This move to an industry-standard PCB fabrication process opened the supply base for PBGA substrates. Today, the industry produces virtually all PBGAs in this manner.

It is not an overstatement to say that the PBGA has taken the industry by storm. At Amkor alone, we have the capacity to produce 4 million PBGAs per week. Worldwide PBGA sales (without silicon value) are now more than $3 billion per year. Chip-scale packages, which are an offshoot of the original PBGA technology, add another $1 billion.

Early Indicators of Software's Role in Wafer Fabs

Bob Reback, President and CEO, Cimetrix Inc., Salt Lake City, www.cimetrix.com

Back in 1982, I was heading a group of hands-on engineers with a passion for robotics. We were installing factory automation at the defense division of Texas Instruments. We bought robots, personally installed them, and wrote our own software. It was fun and a great opportunity for some raw engineers to get their hands dirty in the early days of factory automation.

"Hands on" was also the mode of operation with the first commercial automation efforts in semiconductor fabs. In 1985, I was hired by Thesis in Dallas with the task of installing a fully automated photolithography cell at Northern Telecom in San Diego. It was the first time they were going to take humans totally out of an area of the fab. The novel idea back then was to use robots to load cassettes onto cassette-to-cassette equipment in a photolithography bay that included GCA coat and develop tracks, a Perkin Elmer expose tool, and some resist stripping and wafer inspection. We used five robotic work cells to load the wafer cassettes onto the tools and we even had an innovative idea for material handling where we would deliver cassettes between robot cells.

So there I was, during a fab Christmas shutdown, bolting this first fully automated lithography cell together in the fab chaseway with a guy named Mitchell Weiss, the founder of Programmation. Mitch was personally delivering his first production system. I was also dealing with Jim Pelusi, the product manager from GMF Robotics supplying their first cleanroom robots, and Mitch Tyson, who was division manager for the GCA track equipment. These three all became well-known names in semiconductor fab automation.

Everyone knew that an automated cell needed to have a SECS interface. Companies like GCA had been delivering them for several years, but the fact was that not many people had ever made SECS work. That was a time when fab managers had to beat on suppliers for not delivering what they ordered and paid for, but still equipment arrived and installation engineers had to make do. To solve the problem, we had to make the SECS interface work hands-on.

Looking back at that first robotic photolithography bay at Northern Telecom, it seemed clear then that automation and software control were going to become crucially important for semiconductor manufacturing. In that photobay, controlled by a VAX VMS supervisory computer, we did the earliest APC work that I know of, measuring wafer reflectivity and using that data to change exposure parameters. That photobay was one of the first successful efforts with the SECS interface as we remotely controlled the equipment from the supervisory computer and began "talking" to robots.

I recall thinking then that robots and semiconductor fabs were a good fit because clearly humans had to be taken out of the cleanroom, which has proved to be true. But, once you removed humans, there was going to be a need for a high level of software integration — software was going to play a huge role — to coordinate material handling, remote tool operation, and diagnose problems. These issues are all at the heart of 300 mm fab automation today.

When we installed that photobay at Northern Telecom, a lot of wafer processing was considered black magic with its cadre of gurus continually tweaking a given process. We learned quickly that, by removing humans and letting computers do process control, you could improve the process and eliminate much of the black magic.

The vision seemed clear back in the 1980s. It has obviously taken a while to get humans out of fabs and replace them with robots and other forms of automation, and to achieve a high level of software integration that controls processing and maximizes factory utilization. Could the industry have brought automation on more rapidly? That is hard to answer. Along the way, we did have to shake out mechanical reliability performance with robots and transportation systems, and the standards had to evolve. Perhaps it is just that today, particularly with the surge of 300 mm fabs, the time is right. It is clear, however, that today most suppliers are zeroing in on delivering tools with automation and software that work right out of the box.

Changing Substrates and CMP

Joan Koppenbrink, Vice President, Strategic Alliances and Corporate Marketing, Rodel Inc., Phoenix, www.rodel.com

Perhaps one of the more telling gauges of the dramatic changes that have occurred in the semiconductor industry can be seen in the fundamental starting material for the vast majority of semiconductor devices — the silicon wafer. Just compare the state of the wafer today to these examples from two decades ago:

• Memory disk substrates were significantly larger than silicon wafers. Two-inch wafers were still being used; four-inch were in high volume; and six-inch were state-of-the-art. Disks, on the other hand, were as large as 10 inches.

• Wafer sizes were defined in inches, not millimeters.

• New materials were forecasted to replace silicon for wafers and aluminum for disks, since both were expected to reach their technical limits. GaAs was the material of the future for a very long time.

• Many small players served the industry in addition to a few larger ones.

• CMP meant only "chem-mech polish," the process used to remove lapping damage and create a mirror surface on the substrate wafer.

The semiconductor industry has been ingenious at continuing to make things work. Silicon wafers remain the fundamental semiconductor substrate, and the apparent limitations of silicon continue to be overcome. Two decades ago, it would have been hard to believe that a silicon crystal could be grown to yield 300 mm wafers that meet the flatness, defectivity and contamination specifications for today's state-of-the-art devices.

Just as hard to believe is the level of importance that polishing would ultimately play in the growth of the industry. Polishing rose from only preparing the silicon substrate to become an enabling technology for interconnect fabrication. The use of polishing, more commonly called CMP today, to planarize device wafers so that multilevel interconnect structures could be fabricated on the chip was initially met with significant skepticism. Who would have thought that polishing materials and tools, both significant particle generators, would have a place in the cleanroom? Yet it was this new use of an older technology that was pivotal in the turnaround of the American device companies in the 1980s, and has been critical in the continued growth in the industry on a global basis since then.

In the early 1980s, Japan had overtaken the United States as the leading device makers, and much of the supplier infrastructure had grown and advanced there as well. SEMATECH was founded as an urgent response to regain lost ground in both manufacturing and technology. Around that same time, both IBM and Intel had begun working with polishing pads, slurries and tools to planarize a pre-metal oxide layer to achieve better depth of focus for subsequent lithography steps. The SEMATECH members soon challenged the consortium to develop this use of polishing into a more robust process, and in this way SEMATECH played a major role advancing CMP both within the member base and within the supplier infrastructure, many of which had not served the chipmakers directly in their legacy businesses. The use of CMP became one of the primary drivers that reestablished the semiconductor technical lead in the United States. Of course, today CMP continues to be used on new materials and on more layers, and it has become a standard step for memory and microprocessor production worldwide.

Throughout the semiconductor industry's history, it has achieved technological breakthroughs that would have seemed impossible not that many years before. When limitations are encountered, it is often a combination of incremental improvements and new uses of known process technologies that allow the next-generation devices to be manufactured with the volumes and yields required within the expected time frames. Leveraging fundamental understanding to improve and adapt core technologies to meet the ever-increasing needs of the semiconductor device maker will become even more important competencies for the supplier base as we face the next 25 years.

Meeting Challenges in Test

Neil Kelly, CTO, LTX Corp., Westwood, Mass., www.ltx.com

Like every other sector in the semiconductor industry, semiconductor test equipment (STE) has undergone considerable change over the past 25 years. Keeping Moore's Law on schedule has demanded continuous advancements from STE manufacturers and others in the semiconductor capital equipment industry. The brisk pace of change and intensity of competition have left little room for error or miscalculation.

As shrinking linewidths led to increasing numbers of transistors per die at progressively lower cost, new device applications were enabled. While the processes of fabrication and packaging were able to manufacture and package these new, sophisticated devices, the intellectual property-intensive operations of design and test struggled to respond.

In the test arena, suppliers developed multiple incompatible platforms to test different kinds of devices depending upon the mix of logic, mixed-signal and embedded memory technologies. So rampant was the individualization of test solutions that, at one point, a semiconductor manufacturer might have had as many as three dozen incompatible test platforms. This fragmented test approach led to poor capital utilization among diversified semiconductor device manufacturers; as their device mix changed from month to month, they found themselves simultaneously short of one type of test capacity but with a surplus of another, unless they were willing to overbuy on all of their platforms.

The arrival of systems-on-a-chip (SoCs) in the late 1990s demanded change. None of the current test platforms offered the uncompromising variety of test technology required for these highly integrated devices. To address the challenge of SoCs, a new platform concept was born that incorporated the three previously distinct test technologies — logic, mixed-signal and embedded memory — in a single platform. In addition to providing an SoC test solution, the new platform was able to test all existing device types, since they were essentially no more than subsets of an SoC. This scalable single-platform concept started to render the existing plethora of test platforms obsolete because of the overwhelming economic advantage provided by its improved utilization for all devices.

Today, the concept of single-platform test has taken root, not only with LTX, the original patent holder for single-platform electronic testers, but with other STE vendors as well. Subcontract houses, IDMs and foundries around the world have embraced single-platform systems as more and more customers realize the cost savings and scalability inherent in the architecture of these innovative STE solutions.

But it isn't stopping there. Recent innovations are expanding the range of devices that can be economically tested on a single platform, through extreme scalability of both performance and cost. We are also seeing increasingly compact testers, a result of intense integration efforts and a strong desire to draw the expanses and excesses of Big Iron to a close. With these advancements of today, and those to be introduced over the coming few years, we see a new age for STE, one in which innovation will play the pivotal role in helping our customers succeed.

The Quiet Evolution of Ubiquitous Bond Testing

Malcolm Cox, President and CEO, Royce Instruments Inc., Napa, Calif., www.royceinstruments.com

Over the past 25 years, I have been closely involved with wire-bond and related testing. Today, you do not hear much about this important technology, but bond testing has evolved throughout the intervening years to keep up with the needs of wire bonding that is so instrumental to the industry today.

The origin of the wire-bond destructive pull tester is lost in history. However, destructive bond pull testing was little used outside of research labs until the 1970s. Mainly used for metallurgical investigations, early bond testers were nothing more than a gram gage on a swing arm, with no data capture capabilities. Probably the first production use of wire pull testing was in the early 1970s at Autonetics in Anaheim, Calif. Whit Slemmons designed an electronic nondestruct bond pull tester to support the reliability needs of the Minuteman missile program.

By the early 1980s, nondestructive bond testing had become widely adopted for high-reliability applications such as aerospace and the burgeoning heart pacemaker industry. Initially, there was a lot of concern that a nondestructive test might set the stage for a subsequent bond failure. Eventually, statistically derived gram pull values were accepted that eliminated this concern.

Early commercialization and sales of wire-bond pull testing followed in the United States and the UK. Probably the first electronic bond shear tester was built in 1975 by J.L. Jellison.

In the UK around 1976, I recall visiting a customer in Scotland who was fabricating surface acoustic wave (SAW) devices. He wanted to test how well the device's ball bonds were adhering to thin aluminum. Back at the factory, I suggested how we could adapt our wire-pull tester with a shear tool. The result was a ball shear tester, very crude compared to today's instruments, but this was, to my knowledge, the first commercial instrument capable of measuring ball bond shear strength.

It took production ball-shear testing quite a while to catch on. George Harman of NIST was an early proponent of ball-shear testing, and popularized the test method at many industry conferences throughout the 1980s. The first formal standard for ball bond shear testing was published in 1990 by ASTM, resulting from consultation among several research labs.

I recall suggesting in the early 1980s that one important development needed for bond-shear testing was the ability to control the test height of the shear tool above the bond pad. Eventually, we came up with a technique for touching the shear tool on the surface before lifting the tool off by the required 1-2 µm distance.

Today's tools are, of course, high-precision universal systems that can perform all required wire-pull, bond-shear, bump-shear, ball-pull, stud-pull and die-shear testing. All the additional test methods have been added as interconnect bonding in assembly has rapidly evolved over the past 10 years or so. These can all be done under PC control that provides networkable SPC data management.

As I suggested in my opening comments, bond testers are a bit like the Rodney Dangerfield of the interconnect process. They just "don't get no respect," unlike their glamorous wire bonder neighbors. However high-speed interconnect processes cannot be developed and monitored without exact, dependable bond testing.

Bond testing is not a technology that is standing still. The latest generation of chip interconnect advances, such as ball grid arrays, ultrafine pitch and stacked-die wire bonding, all impose fresh challenges on bond testing, which we enthusiastically meet.