Breakthrough in Spin-Wave Research
Peter Singer, Editor-in-Chief -- Semiconductor International, 6/1/2006
Engineers at UCLA's School of Engineering and Applied Science announced a critical breakthrough in semiconductor spin-wave research. Engineering adjunct professor Mary Mehrnoosh Eshaghian-Wilner, researcher Alexander Khitun, and professor Kang Wang have created three novel nanoscale computational architectures using a technology they pioneered called "spin-wave buses" as the mechanism for interconnection. The three nanoscale architectures are not only power-efficient, but also possess a high degree of interconnectivity.
"Progress in the miniaturization of semiconductor electronic devices has meant chip features have become nanoscale," Wang said. "Today's current devices, which are based on CMOS, can't get much smaller and still function properly and effectively. CMOS continues to face increasing power and cost challenges."
In contrast to traditional information-processing technology devices that simply move electric charges around while ignoring the extra spin that tags along for the ride, spin-wave buses put the extra motion to work transferring data or power between computer components. Information is encoded directly into the phase of the spin waves. Unlike a point-to-point connection, a "bus" can logically connect several peripherals. The result is a reduction in power consumption, less heat and, ultimately, the ability to make components much smaller, as no physical wires are actually used to send the data.
"Design of nanoscale architectures for computing is a very new area, but an important one for the future," Eshaghian-Wilner said. "In order to produce effective nanoscale devices, we need to actively look at new low-power designs that can have efficient interconnectivity and allow scaling beyond current barriers."
UCLA engineering's team contends that the creation and detection of spin-wave packets in nanostructures can be used efficiently to perform massively parallel computational operations, allowing for the design of the first practical, fully interconnected network of processors on a single chip. This breaks with currently proposed spintronic architectures, which rely on a charge transfer for information exchange and show significant interconnect problems.
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