Industry News: Flip-Chips Changes, TSVs, Low-Power 32 nm
Staff -- Semiconductor International, 8/1/2008
Flip-Chip Changes on the Horizon
Flip-chips haven't changed much since being invented by IBM (Armonk, N.Y.) in the early '60s. It's simply a method of interfacing with an electronic chip. As George Riley, managing director of FlipChips Dot Com (Worcester, Mass.), aptly describes it: The basic flip-chip concept is to take a chip, place conductive bumps on its connection points, flip it over to put it facedown and directly attach it to the circuit. Flip-chips get rid of all excess packaging while also offering benefits, such as high-frequency operation, low parasitics and a high I/O density. They're used in almost every hot consumer gadget imaginable, ranging from cell phones and pagers to MP3 players and digital cameras.
But some very interesting trends are emerging in the flip-chip arena, with several potential changes on the horizon.
To start with, demand for flip-chips is on the rise thanks, in part, to a spike in gold-bonding wire costs. "Significant trends are taking place because the cost of gold wire is increasing," explained Raj Pendse, STATS ChipPAC's (Singapore) vice president of flip-chip and emerging products. "Mobile products or platforms that traditionally used wire bonding, 3-D and stacked die are now an area in which we see future growth potential. A couple of performance reasons are also helping drive a shift to flip-chips: You can miniaturize better with flip-chip, and the silicon used in mobile applications is becoming more dense [higher I/O density]. Rising gold prices have pushed that crossover point to a lower pin count, though. Mobile and handheld applications are typically in the 200-700 pin count range. The crossover point for flip-chip used to be around 1000 I/O, where most of the computing and game consoles are. But now it's come down to about 500 I/O. From a broad performance and cost perspective, I'm seeing a very big shift into the 200-700 pin count applications — starting with mobile products for cell phones, digital cameras and other handheld products. The way the industry is responding to rising gold costs is to move to copper wire or finer-diameter wire bonding. Or considering making a move from wire bonding to flip-chip instead."
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| Demand for flip-chips, such as this flip-chip ball grid array (BGA) system-in-a-package (SiP), is on the rise. (Source: STATS ChipPAC) |
FlipChip International (Phoenix) is also seeing a shift from wire bonding to flip-chips. "There definitely seems to be a continued trend of migration toward flip-chip, driven by the cost of gold wire," noted Ted Tessier, FlipChip's CTO. "I don't think we're seeing the complete effect of this happening yet, because there's a lot of work required to transition from products that are primarily wire bonded over to flip-chip. But it appears to be underway."
And Pendse pointed out that design methodology for chips is very different when comparing wire bonding and flip-chip. "With the new silicon generations, starting at 45 nm, many of our customers are deciding that it might not be worthwhile to sustain two kinds of design methodologies for the same application. If there is a small cost difference one way or another in the total cost of the package, they are choosing to design new silicon directly into area-array layouts for flip-chip interconnection. While it won't have a big impact on 2008 or 2009 revenue, it should have an impact on 2010 revenue. To some extent, this is being accelerated by the gold wire cost issue," he said.
Yet another trend emerging is related to the growth in embedded die technologies. "We're doing some work to support embedded die technologies," Tessier said. "At this point, we're customizing die for embedding and it seems like the highest-volume application coming along within the next year or two will be related to embedding devices, possibly passive devices like silicon, into cell phone boards and laminate substrates."
Changes on the horizon for flip-chips? The European Union's RoHS lead-free regulations and new halogen-free requirements are bringing significant technology-related changes. "The bump in flip-chips will be required to be lead-free in the near future," Pendse said. "There were RoHS exemptions for flip-chips, so the bump didn't need to be lead-free. Under that exemption, which will expire in 2010, many companies didn't change the bump to lead-free. Companies that made the transition are using copper instead. As the bump goes lead-free, the bill of materials is also going halogen-free, which includes substrates that are not halogen-free today. The lead-free change is creating many problems. For example, the cost of bumping is different and the reliability of the package isn't on par with the old structure. Materials for underfill need to be different to match with lead-free bump properties, so numerous new issues are cropping up. It's spawning development in underfill materials, substrates, etc. And determining which lead-free composition is the best one has been a big challenge."
Another challenge is how to make a cost-effective substrate for a flip-chip package. There's a drive to migrate to flip-chips for many reasons, but also because of the need to streamline the design. Flip-chip substrates today cost roughly 2× as much as wire-bond substrates. To make a lower-cost substrate, the industry is looking at new ways to efficiently route and design interconnection of the chip to the substrate. "You cannot route any signals on the top layer of the substrate, so it requires multiple layers," Pendse said. "So we're now looking at ways to make that fine I/O interconnection to get enough routing space on the top layer of the substrate and keep the layer count at 2–4 layer with laminate in design rules. The substrate will become closer to a wire-bond substrate. This is going to be a major change within the next two years."
And of course, how do flip-chips fit into 3-D integration? "We've come up with a way to combine flip-chip and wire bonding in stacked integration that we call a hybrid flip-chip package," Pendse explained. "Since you cannot just put four flip-chips on top of each other because there's no mechanism to do that today, we've combined wire bonding and flip-chips to convert the most I/O dense area to a flip-chip and put it into the bottom and put wire-bond die on top of it. It comes with its own bag of issues, however. How do you create a surface finish? One on which you can wire bond and do flip-chip as well. How do we combine underfill and wire bonding? This is a new realm of packaging. We're doing a lot of work in this area right now. The move to 3-D packaging with through-silicon vias is actually a good fit for flip-chips because when you make TSVs, you can put one flip-chip on the back of another flip-chip."
It's been years in the making, but flip-chips are finally being widely adopted in the industry. "Wafer-level chip-scale packaging {WLCSP] has been strong the past several years and is continuing to grow," Tessier said. "Flip-chips are also starting to be used more in high-volume SiP for wireless applications. And we're seeing newer bumping technologies like the copper pillar bump really take off."
As far as how the flip-chip market is performing, Jim Walker, vice president of research, semiconductor manufacturing, Gartner (Stamford, Conn.), said that continued drive to integration through increased density and improved performance is playing into the demand for flip-chip-based packages.
"Many of the substrate suppliers for IC packages and flip-chip interconnects are optimistic about the second half of 2008," Walker elaborated. "The PC market demand now looks stronger than expected earlier in the year, so chipset and graphics card markets that use flip-chips should improve in the second half. Orders for flip-chip substrates used in game consoles and continued growth in digital TV will further increase the adoption of flip-chip in the second half as well. Orders for high-end cell phones and PDAs using flip-chip CSP are stronger than other applications. And the use of flip-chip substrates based upon bizmaleimide-triazine used in FPGA devices increased in Q2, and will continue to grow in the second half. All of this increased growth bodes well for the flip-chip market. The industry hasn't seen much increase in package substrate capacity in the past two years, which will result in a tighter supply with more stable prices."
— Sally Cole Johnson, Contributing Editor
TSV Apps Need TSV Tools
While key applications in CMOS image sensors and stacked memories continue to drive 3-D technology, a significant need from the tool side is still unmet: production-worthy throughputs. The technologies used to create and fill through-silicon vias (TSVs) — whether it be etching, plating or chemical mechanical planarization (CMP) — need to perform at much higher rates to make 3-D technology cost-effective, according to Kyle Kirby, engineering supervisor at Micron Technology (Boise, Idaho). He spoke at Semitool's latest Peaks Symposium on Electrochemical Processes for Microelectronics, held in Kalispell, Mont. "We need CMP slurries just for TSV," Kirby said. "Etching the vias is a slow process and plating, too, needs to be speeded up as much as possible."
Of course, DRAMs are an extremely cost-sensitive market, so Micron is investigating several different 3-D schemes, including via-first and via-last methods, laser drilling and reactive ion etching (RIE), as well as polysilicon or copper fills. "In what we call the via-first first approach, polysilicon vias are fabricated into the substrate before any of the device is built up," Kirby said. "Wouldn't it be interesting to be able to purchase substrates with TSVs all ready to go?"
Chip stacking with interconnecting TSVs is definitely in DRAM's near future, just because the performance of even stacked memory packages is limited. Kirby mentioned that tungsten can currently fill higher-aspect-ratio vias than copper, but copper is more prevalent.
Jan Vardaman, president of TechSearch International (Austin, Texas), also presented on TSV technology and applications. "Perhaps the most controversial is NAND flash, because memory manufacturers are saying that 3-D integration at an existing node will be less expensive than going to the next node. Now, it's important to note that not everybody agrees with that," she added, pointing out that Intel (Santa Clara, Calif.) and Spansion (Sunnyvale, Calif.) have said they will not use TSVs in flash because they are too expensive. On the other hand, NEC Corp. (Tokyo), Oki Electric (Tokyo) and Elpida Memory (Tokyo) expect to have TSVs in commercial memory production by 2010. Samsung (Seoul, South Korea) is also aggressive with TSV technology, having announced that it is combining 2 Gb DRAMs to create a smaller, faster 4 Gb DIMM (dual inline memory module) that uses less power. Vardaman also pointed out that Tezzaron (Naperville, Ill.) and Chartered Semiconductor Manufacturing (Singapore) announced ramp of a high-speed SRAM product that is double stacked to create a 144 Mb SRAM replacement product.
Large memory capacity in a limited area
Reducing cost through conventional scaling is less effective at increasing the capacity for a given chip size, according to Vardaman. What's needed for cost reduction is the vertical stacking of NAND flash wafers on wafers. She showed a cross-section of polysilicon TSVs interconnecting NAND chips.
Field-programmable gate arrays (FPGAs) also need TSV solutions, Vardaman said. FPGAs typically have large die, so long intrachip wire lengths create delay problems. Excessive wire lengths make it difficult to increase chip-operating frequency. Also, repeaters are often used, which further increases the chip footprint. Using 3-D TSV technology, circuits are split up into smaller units and stacked for overall reduced chip area, fewer repeaters and shorter wires for less overall delay.
In the case of high-speed microprocessors, TSV use is expected to come later because new architectures must first be developed. A possible time frame, according to Vardaman, is around 2014. Despite Intel's reluctance, it appears that TSVs will need to be adopted for microprocessors eventually because of the need to scale memory bandwidth. "The busses must become wider to deliver necessary 10–30 Gb/sec memory bandwidth, and multicore systems will require 100 Gb/sec memory bandwidth," she said.
In addition to the tools needing to be honed specifically for TSV technology, there are design challenges, which Kirby elaborated on a bit. These have to do with real estate, routing and proximity. "You do not want your vias to be close to any other functionality, and it is desirable to have a universal pattern," he said, adding that all die should be patterned using the same mask to reduce cost as much as possible. In processing and packaging, thermo-mechanical stresses must also be considered, both axial and circumferential.
Both speakers relayed that there will be different TSV solutions for different device technologies; no one approach will ultimately satisfy all applications.
— Laura Peters, Editor-in-Chief
IBM vs. TSMC for Low-Power 32 nm
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| IBM and its alliance partners described a 32 nm technology for low-power applications at the 2008 Symposium on VLSI Technology. |
IBM Corp. (Armonk, N.Y.) has traditionally saved its competitive juices for Intel Corp. (Santa Clara, Calif.) in the race for high-performance transistor performance. This year, however, IBM engineers returned home from the 2008 Symposium on VLSI Technology, held in Honolulu, to argue that its adoption of a gate-first high-k/metal gate implementation at the 32 nm generation will put IBM and its partners ahead of Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC, Hsinchu, Taiwan).
With the low-power mobile market space as the high-growth market opportunity, IBM Vice President Gary Patton highlighted the differences between the high-k/metal gate process that IBM and its Fishkill process development partners will offer compared with TSMC's announced plans to introduce a 32 nm transistor with a nitrided oxide (SiON) dielectric and polysilicon gate.
TSMC unveiled its 32 nm low-power transistor at the 2008 International Electron Devices Meeting (IEDM) last December, and discussed its 32 nm rollout plans again in April at the TSMC technology symposia in several U.S. cities. For low-power and general-purpose applications, TSMC plans to stick with a conventional gate stack to keep costs down, but will adopt aggressive embedded silicon germanium (eSiGe) strain techniques, according to its IEDM presentation. TSMC plans to introduce a high-k dielectric for the high-performance 32 nm process it is developing for the Sun microprocessors.
Patton said TSMC has it all backwards, arguing that "poly oxynitrides are going to be quite a bit more expensive than high-k/metal gate at 32 nm." Companies that use poly oxynitrides at 32 nm will have to go to a triple oxide process, he said, adding that "to get anywhere near decent performance, they will have to go to a thin oxide, which increases leakage." Embedded SiGe strain engineering will raise costs, he argued.
Mukesh Khare, project manager for high-k/metal gate technology at IBM, said, "We are introducing one big element: high-k. For a company that sticks with an oxide poly approach, they have to throw in the kitchen sink, putting in stress liners and other stuff. It is more cost-effective to do one big element than a bunch of smaller elements to get to the same performance target. With our approach, we do not need to add SiGe strain engineering for the PMOS for low power. TSMC will be throwing in all kinds of strain engineering, which is contrary to what you are trying to achieve for a low-cost mobile product, where you want a very low-cost process."
The IBM engineers said that because high-k adds such advantages at 32 nm, many customers will skip the 45/40 nm generation and go directly to a 32 nm process. "Some customers may bypass the 45 nm generation in order to take advantage of high-k," Patton said.
Khare said, "Our integration approach allows us ground rule compatibility from 45 or 40 to 32 nm and migrating forward to 28 nm. That is very different from other methods of high-k/metal gate, where you have to be very careful of ground rules and introduce more polishing."
With the Fishkill partners competing with TSMC for share of mind at the lucrative 32 nm mobile market, IBM engineers have become aggressive in claiming power advantages. In December 2007, IBM reported that it had created a test 32 nm SRAM. Last April, it said it was ready for customers to begin 32 nm designs.
An Steegen, the 32 nm bulk CMOS project manager at IBM, said high-k/metal gate allows IBM to reduce the low-power oxide thickness by ~10 Å to a 14 Å inversion thickness (Tinv). The thinner gate oxide improves performance, allows the gate length to be reduced to 30 nm, and keeps the SRAM Vmin to the optimum level. Contacts can be placed closer together without danger of shorting effects.
At the 32 nm generation with an oxynitrides technology, short-channel effects become onerous, she said. "High-k is key to controlling a short channel, which is a big problem when still using oxynitrides.
IBM is offering a multi-project wafer shuttle program, with the run scheduled for September sold out in May. A second shuttle is planned for December. IBM and its Fishkill partners plan to begin manufacturing the 32 nm low-power process in the second half of 2009. Patton said, "Our 32 nm process makes it easy for customers to migrate their IP from previous generations. For one thing, transistor drive current ratios are very similar to what they are at 45. If a design is port to a 32 nm process with a nitrided poly gate stack, the drive current ratios drop significantly and that would require some significant redesign work."
At the VLSI meeting in Honolulu, IBM engineer Xian Chen described a 32 nm technology, with co-authors from Freescale Semiconductor (Austin, Texas), Chartered Semiconductor Manufacturing Ltd., Infineon Technologies AG (Munich) and Samsung Electronics Co. (Seoul, South Korea). Compared with an SiON poly, a 30% ring oscillator delay reduction has been demonstrated with high-k/metal gate devices. A 40% threshold voltage mismatch reduction has been shown with the Tinv scaling," Chen wrote.
Acknowledging concerns that a high-k/metal gate process introduces high costs, Chen said, "Less than 3% total process cost is added with high-k/metal gate compared with a poly-SiON gate stack. The use of a hafnium-based high-k gate dielectric allows us to maintain a low gate leakage of &0.1 A/cm2 while continuing to provide substantial room for EOT scaling."
The SRAM cell size is 0.157 μm2. NMOS/PMOS drive currents were 1000/575 μA/μm at 1 nA/µm off-current and a 1.1 Vdd, which can be scaled to 1.0 V for active power reduction.
Steegen said customers will continue to use multiple power rails and other design techniques to control standby power. The insertion of high-k/metal gate means active power will be improved, allowing 32 nm customers to employ dynamic voltage scaling to manage active power. "The big issue at 32 nm is active power management and control. High-k gives us enough margin on performance that we can book that by Vdd scaling. We can meet certain performance requirements at 0.9 V and get active power savings," she said.
— David Lammers, News Editor
