Air Gaps: Unlikely Becoming More Likely?
Laura Peters, Editor-in-Chief -- Semiconductor International, 4/23/2008
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The upcoming International Interconnect Technology Conference (IITC), held in Burlingame, Calif., June 1-4 will once again feature papers on the use of air gaps as a low-k dielectric. But unlike the papers of years ago, air gaps seem to be emerging out of the pure research phase, becoming possible, even likely, to one day be used in production devices.
As stated in the latest International Technology Roadmap for Semiconductors (ITRS), “At &22 nm, feature size effects, such as electron scattering from grain boundaries and interfaces, will continue to increase the effective copper resistivity. Ultralow-k dielectrics may be replaced by air gaps in selective areas.”
Two companies propose sacrificial approaches to air gap formation in the pre-conference material. Toshiba (Tokyo) builds a 10 metal level interconnect with sacrificial polyarylene (PAr) interlevel dielectric (ILD, Fig. 1). In a single high-temperature step, the PAr is removed, leaving behind air gaps. STMicroelectronics and CEA-Leti researchers in Grenoble, France, will also report on the use of a sacrificial material, SiO2, which is removed using hydrofluoric acid (HF).
Key goals in the Toshiba work, to be presented by N. Nakamura and colleagues, were maintaining cost-effectiveness in a multilevel build and solving the accommodation of misaligned vias. Using PAr at the line level and SiOC at the via levels, through holes were drilled from the top metal to bottom PAr level. Then the PAr is removed from the structure by reactive ion etching, and the air channels are then plugged with spin-on dielectric.
| 1. Polyarylene (PAr) dielectric is sacrificially used where RC is critical. In one high-temperature step, the PAr is removed. (Source: Toshiba) |
Meanwhile, STMicro and CEA-Leti researchers locally integrated air cavities with an existing, specific structure that was known to be mechanically stable. R. Gras and co-workers introduced air gaps at both the line and via levels into two levels of a three metal level, 65 nm process. They built the interconnect structure on 300 nm wafers with oxide (SiO2) dielectric. They then deposited a SiCN capping layer and used a non-critical mask layer to pattern through holes. In a vacuum environment, HF was applied, which etched away the underlying oxide to create air gaps. SiCN was again deposited to close the through holes. Resistance capacitance (RC) delays were reduced by up to 45%, and there was no damage to the copper lines. The researchers reported a slight increase in electromigration, but lifetime targets were met.
| 2. In a 65 nm, three metal level scheme, air gaps are formed in two levels by patterning apertures into the SiCN capping layers and etching with HF. (Source: STMicroelectronics) |
