Through-Silicon Vias: Ready for Volume Manufacturing?

IDMs, foundries and packaging houses are now developing capabilities for through-silicon vias, but more work needs to be done to address manufacturing costs.

Peter Singer, Editor-in-Chief -- Semiconductor International, 3/1/2008

Much has been written about the many drivers behind 3-D integration, a technology where chips are thinned, stacked and interconnected, which greatly increases density as well as performance.^1–4 Chip-to-chip connections have, to date, been accomplished with wire bonding, sometimes to eight or more stacked die, but this is limited in terms of the number of connections (I/Os) and electrical performance.

Volume manufacturing will require the use of tools, such as online chemical monitoring systems, to monitor and control the chemical components of the copper plating bath. (Source: ECI Technology)

In the near future, perhaps within the next two years, the industry is likely to shift to an approach where the connections are made directly through the silicon. Through-silicon vias (TSVs) are already being put into production for CMOS image sensors, where the active silicon area is bonded onto glass and contacted from the backside. TSVs for stacked-chip applications are well into the development phase, and are likely to be in production by 2010, according to Jan Vardaman, President of TechSearch International Inc. (Austin, Texas; see "

What's Delaying the Adoption of 3-D TSV?

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There is no clear-cut approach to TSV manufacturing. Those interviewed for this article see active development programs across the board at IDMs, foundries and outsourced semiconductor assembly and test companies (OSATs). "All the packaging approaches, including the stacked-chip approaches that use through-silicon vias, are in their infancy," noted Chris Case, CTO of The Linde Group (Munich, Germany) and chairman of the International Technology Roadmap for Semiconductors (ITRS) Interconnect Technology Working Group in a recent Semiconductor International webcast.⁵ "They're mostly being done in development facilities. The technical challenges of producing those vias are more or less solved. The real challenge is achieving satisfactory costs of implementing a relatively new technical approach." Case said that the most recent update to the ITRS, which was released in December 2007, presents a view of potential solutions for 3-D packaging.

There seems to be little agreement, however, in terms of relatively simple things such as the size of the via holes, thickness of the wafers, whether a via-first or via-last process is better (although OSATs have no choice but via-last), or even what type of metal is the best choice. Electroplated copper is the leading choice, but there's also interest in tungsten deposited by chemical vapor deposition (CVD). People are even looking at vias with electroplated "liners" filled with a conductive epoxy paste, similar to what is used to contact high-power GaAs devices from the backside.

The ultimate success of any TSV process in volume manufacturing, of course, largely depends on cost. "The biggest challenge in the long run is the cost of the manufacturing," said Peter Bratin, vice president of ECI Technology (Totowa, N.J.). "Right now, it's an enabling technology, so you can overlook a lot of factors." In the electroplating area, for example, companies trying to fill large vias with high aspect ratios are finding that it may take hours to do so. "Because the via is much larger than the trenches you're dealing with in the damascene process — the electrodeposition mechanisms just aren't exactly the same," Bratin said. "The chemicals and plating additives need to be improved to better suit the via filling. Tight process control over all chemicals is a must. A lot of work is being done by a number of chemical suppliers and universities to come up with the improved formulations of the additives." Consumption of the chemical additives is also critical.

One of the major goals of the EMC3D consortium, which is focused on developing integrated solutions for TSVs, is to get the cost for the entire process to $200/wafer.⁶

In terms of which type of company will eventually take ownership of the TSV process, Semiconductor International 3-D blogger, Phil Garrou, who is also editor of the 2008 Wiley-VCH text, Handbook of 3D Integration, sees traditional IC foundries developing via-first front-end-of-line (FEOL) polysilicon-filled vias or back-end-of-line (BEOL) copper- or tungsten-filled vias, while traditional packaging houses, such as Amkor (Chandler, Ariz.), Advanced Semiconductor Engineering (ASE, Kaohsiung, Taiwan) and STATS ChipPAC (Singapore) will be developing post-BEOL, via-last, copper-filled TSV technologies. "You'll see more of the via-last technologies entering the marketplace first until the foundries release their processes for chip designers to work with. Then, it is likely that the via-first technologies, where the vias are designed in and manufactured by the foundries, will begin to take significant market share" Garrou said.

TSV processes

Many believe that the lowest-cost, best-performing solution will be one that leverages the equipment, materials and technology developed for mainstream semiconductor manufacturing, liberally combined with experience from MEMS, printed circuit board (PCB), high-power devices and other volume processes.

In this scenario, the via or hole is etched through the silicon (and often many overlying layers of metal and dielectric) using a deep reactive ion etching (DRIE) process. This hole is then typically lined with a dielectric "sleeve" deposited by CVD. Then, much as with copper dual damascene processes, a diffusion barrier and copper seed layer is deposited by physical vapor deposition (PVD), and the hole is filled by electroplated copper. Companies such as Alcatel Micro Machining Systems (Annecy, France), Aviza Technology (Scotts Valley, Calif.), Lam Research Corp. (Fremont, Calif.), Semitool (Kalispell, Mont.) and many others have developed processes specifically tailored for TSVs. This article will focus on some of the unique challenges and solutions encountered in these processes, and what experts see as challenges that have yet to be overcome, particularly related to cost.

It's important to note, though, that other types of processes are also being developed. Wet etch processes have been developed to create via holes, and laser drilling is also a viable alternative. A good overview can be found on the EMC-3D website, and at the upcoming IMAPS Device Packaging Conference, to be held in Scottsdale, Ariz., March 17-20. Similarly, TSV processes are not limited to device chips, but can be used for silicon "interposer" subsrates as well (see "Technology Platform Integrates High-Performance SiP Modules").

One of the main issues to consider in TSV processing is when and where it will be done, and there are two main choices. The first — called "via-first" — is to design it in at the start and then physically create the via before CMOS or BEOL metallization. With via-first, the dimensions of the vias are typically smaller (5–20 μm wide), with aspect ratios of 3:1 to 10:1. This is the approach typically taken by IDMs. The other alternative — "via-last" — is to create the via after BEOL or bonding, essentially when the wafer is finished. In this case, the processing can be done by the IDM or packaging house. The CDs in this case are wider (20–50 μm), with equally challenging aspect ratios of 3:1 to 15:1. Steve Lassig, senior engineering manager, product marketing at Lam Research, said that there is almost two orders of magnitude of difference in feature sizes for TSVs now in development. "What we're seeing is a wide range of requests from customers to demonstrate through-silicon via from as small as 1 μm that may only be about 10 μm deep to, on the other end, 90-μm-vias more than 400 μm deep."

Part of the reason for the wide disparity in via sizes is that packaging houses (which, by nature, are doing a via-last process) typically have access only to lower-tech PVD equipment for depositing the barrier/seed layer, and these tools are not capable of handling aspect ratios much beyond 3:1 to 5:1. Because the vias need be fairly deep through thicker wafers in the 200–300 μm range, the via needs to be correspondingly large (i.e., 100 μm wide) to have a low aspect ratio. "You can get the barrier/seed in and fill it, but it's going to be cost-prohibitive in order to get it into any kind of manufacturing situation because of the process time," said Tom Ritzdorf, director of ECD technology at Semitool. "You also need to be very worried about the thermal characteristics with such large vias. Because of the CTE mismatch between copper and silicon, you're likely to have reliability problems. It could be as bad as cleaving the wafer when you anneal it," he said. The route to smaller vias with higher aspect ratios is either through investment in more advanced PVD equipment or through "seed-layer enhancement" technologies developed by electroplating companies.

Ritzdorf said that the EMC3D consortium has been focused "a little bit more" on the via-first process. "The nice thing is we've all dealt with this technology enough that it really wasn't much of a problem to run wafers and get TSVs that were filled on the first lot we ran," he said. "The place where via-last comes in [for what happens to be the first adoption of TSVs] is for CMOS image sensors. Since it's the first real application, that obviously makes it important to us," he said.

Wafer thinning

The formation of the metal-filled holes is only part of the TSV process. The chips must also be thinned and bonded together. Thinning is done by grinding, chemical mechanical planarization (CMP) or by a wet chemical process. A silicon or glass carrier is typically used here, where the wafer is turned upside down and temporarily bonded to the carrier. After processing, the wafer is debonded with ultraviolet (UV) light (or a laser) in the case of glass carriers, or with a thermal process (heating on a thermal plate) in the case of silicon carriers. 3M (St. Paul, Minn.) offers a temporary bonding adhesive used for the UV release approach, while Brewer Science (Rolla, Mo.) and EV Group (EVG, Schaerding, Austria) have teamed up to develop an adhesive that debonds thermally. Steve Dwyer, vice president and general manager of EVG NA, said that the main advantage of using silicon as a carrier is that it is a perfect thermal expansion match to the device wafer. "Otherwise, you risk introducing thermal mismatch stress into your thinned wafer, which is not a good thing," he said. He also said the thermal debonded adhesives could withstand higher temperatures during processing.

1. Fully plated TSV, 10:1 aspect ratio. (Source: Aviza Technology/Cubic Wafer Inc.)

David Butler, director of the marketing, PVD/CVD/etch business unit of Aviza Technology, has worked with glass carriers and said that processing temperatures vary, with the dielectric deposition typically being the highest. "The deep silicon etch process is low temperature, no problem. The metal, as well, is cold, that's fine. The dielectric also has to be low temperature without impacting coverage or electrical properties, so that means that traditional processes have limited valve. We are working with low-temperature variants of current schemes and looking at alternatives. Presently, the sort of number that people will say is worst case or max temperature is around 250°C. Others say that may be okay for a few months, but we quickly want to get below 200°C to 150°C."

The overriding issue in chip stacking is whether to use a wafer-to-wafer, die-to-wafer or die-to-die approach. Wafer-to-wafer is the easiest and most cost-effective, but only if the yield on both wafers is high. The risk of bonding a bad die to a good die is reduced with the other approaches, but the cost of handling and processing is greater.

2. High-aspect-ratio TSV etched with the Bosch process and lined with ionized PVD. (Source: Aviza Technology)

Silicon etching

The when and where of the TSV process — via-first or via-last — also determines the side from which the via is to be etched (or drilled). With via-last, the wafer is completed and the option exists to etch from the top or back of the wafer after thinning.

Via-first wafers are typically full-thickness wafers (650 μm thick), etched only partially down, ~10% of the way into the wafer (Fig. 1). This is typically a "blind" etch in that there is no measurable end point. It's simply a timed etch.

A common method of deep silicon etching is the "Bosch" process, named after the company by which it was originally developed. "The Bosch process is a way of being able to etch deep structures into silicon with vertical or near-vertical sidewalls and with very high selectivity to masks," said Dave Thomas, marketing director of etch products for Aviza

3. Resputtering by ionized PVD gives continuous coverage over heavily scalloped sidewalls. (Source: Aviza Technology)

Technology. "Those are all the positives. The negative to the Bosch process is that because it's a step-wise isotropic etch and polymer deposition, continuously switched throughout the entire process, maybe hundreds of times, you get these sideways etches into the sidewall, which we refer to as scallops." Figure 2 shows a deep (150 μm) hole etched with a fairly high etch rate of ~20 μm/min. Note some scalloping near the top and a slight bow in the center of the via (which are perfectly acceptable). Figure 3 shows a close-up of the scalloping. "You want to push the TSV etch to the point where it has the best possible cost of ownership, but is not so rough and scalloped that you can't it handle it thereafter," Thomas said.

Lassig agrees: "Sometimes the Bosch process will have heavy scalloping. You have to understand that process very well to minimize the effect of the scalloping. We've been able to demonstrate fairly smooth scalloping. You can still see it, but it's not very heavy and certainly allows the integration to go forward." Figure 4 illustrates the Lam Research TSV process, indicating high uniformity between vias at the center and edge of the wafer.

4. Examples of TSVs with 30 µm CD etched through 1 µm aluminum, 3 µm oxide and 70 µm silicon in one wafer pass (center and edge of a 300 mm wafer). (Source: Lam Research Corp.)

Etch specialists are quick to point out that although the bulk of the material being removed is indeed silicon, there is typically an overlying set of materials that can be a challenge. "The term through-silicon via sounds like you're just etching silicon, but in reality, in almost every case, the via is going through at least a dielectric layer, which may be anywhere from half a micron to 5 μm of whatever was on the wafer, and it may even include conductive layers," Lassig said.

5. 15-µm-diameter via opened through back-end oxide comprised of 40 discrete layers. (Source: Aviza Technology/Cubic Wafer Inc.)

Thomas added, "You can imagine on an 11-layer device that there are all sorts of different dielectric materials. There are 40 different discrete layers we're etching through continuously and then stopping on the silicon surface." This is well illustrated in Figure 5. "We had to open the oxide via before we reach the silicon," Butler explained. "You can see on the left and right of the big well the little 10–11 metal layers that came from this 90 nm or 65 nm device. We've sunk a big via through the oxide that hits the silicon underneath." In this case, the whole top surface acts as a hard mask for the TSV etch.

The main challenge with TSV etching is perhaps not a technical one, but one of balancing the costs with performance. "The big challenge for the industry is how do you make this cost-effective? How do you make it high productivity? Certainly, silicon etch rate is important, but being able to etch with a decent profile where you can fill it without voids and get good electrical results is really the big challenge," Lassig said.