3-D Equals Two Generations of Scaling
North Carolina State Professor Paul Franzon said the need for 3-D ICs is becoming more acute as CMOS scaling improvements (according to MIT projections) halt at the 32 nm node and beyond. However, 3-D yield and design challenges remain, according to IBM and Cadence technologists who participated in a IEEE Components Packaging and Manufacturing Technology (CPMT) workshop in Austin, Texas.
Philip Garrou, Microelectronics Consultants of North Carolina, Research Triangle Park, N.C. -- Semiconductor International, 4/2/2009
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North Carolina State University Professor Paul Franzon said gains from conventional CMOS scaling appear to be running out of steam, providing an urgent need for 3-D interconnects to pick up the slack.
“3-D IC buys you two generations of scaling,” Franzon said at an IEEE Components Packaging and Manufacturing Technology (CPMT) workshop in Austin, Texas. He referenced a study by the MIT Microsystems Technology Labs that indicates — from the 32 nm CMOS generation onward — intrinsic transistor performance will not improve unless parasitic capacitances are significantly reduced.
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| Beyond 40 nm, parasitic capacitances significantly impact transistor delay. (Source: A. Khakifirooz, “The Future of High-Performance CMOS: Trends and Requirements,” 38th European Solid-State Device Research Conference, September 2008) |
Mike Shapiro, a technology strategy manager at the IBM Systems and Technology Group, said IBM is focused on developing a rock-solid through-silicon via (TSV) process. IBM managers have said TSV yields must equal on-chip interconnect yields for the eventual economics to make sense.
Shapiro said the IBM-backed Nanoscale & Packaging Technology Center planned for upstate New York will play a role in 3-D development. IBM has agreed to invest $1.5B and the state of New York another $50M in 2009, despite the sluggish economic times. Shapiro said a key program at the center will be “developing 3-D technology for use in future-generation products, which are being developed to take advantage of 3-D.”
Cadence Digital IC Technologist Vassilios Gerousis said Cadence is engaged with “leading commercial customers in 3-D software development.” Cadence has developed a basic set of tools and a design methodology for 3-D, Gerousis said, adding that Cadence and a leading 3-D customer taped out two 3-D stacked chips on a 45 nm process in 2008.
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